Abstract: A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of "SET", "AND" and "OR" functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register.

Abstract: A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered.

Abstract: A mechanism for an automated system to allow a user of the system to demonstrate his legitimacy by demonstration of secret knowledge. The mechanism is resistant to compromise by observation of its use. An array of symbols is presented to the user and the user is required to manipulate several symbols at once until assigned key symbols are manipulated into predetermined states. Doing so effectively prevents an observer from determining which symbols are the ones of interest. For example, pushing a button might cause several symbols in the array to exchange their positions. The user continues to do this, having, perhaps, to use several different buttons, until a certain subset of the symbols appears in certain locations within the array. (In this example, the arrangement of this subset of symbols is the user's password or PIN.

Abstract: A safety switch is provided with an auxiliary contact that is actuated by the heel of the bail. The heel actuation enables the auxiliary switch to be easily installed and wired and enables the same actuator and bracket to be used for varying sizes of bails.

Abstract: An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the facilities are manipulated. This classification of instructions into types allows for the amount of checkpoint data to be minimized while allowing recovery to be generalized into broad algorithms instead of handling each operation independently. Furthermore, by applying this classification technique to various phases of execution (recovery windows) of instructions which modify system facilities before they complete, these instructions can also be retried with a minimum of hardware and algorithms.

Abstract: In a tightly coupled multiprocessor system, I/O interrupts are distributed to respective processors in accordance with load conditions of the processors without partiality to any one processor. Interrupt arbitration circuits provided in respective processors receive an interrupt request from an I/O device, effect interrupt arbitration using a parameter indicating the load condition of each processor as a first interrupt priority. If the arbitration fails to determine a sole processor, additional arbitration finally selects a sole processor P on the basis of the second interrupt priority which is varied circularly.

Abstract: An alternate instruction architecture which uses the preexisting dataflow and hardware controlled execution units of an otherwise conventional pipelined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These milli-mode instructions augment the standard "user visible" architected instruction set (which in the preferred embodiment is the System 390 instruction set). Millicode routines can intermingle the milli-mode only instructions with standard system instructions to implement complex functions. The set of instructions available in milli-mode can be considered to be an alternate architecture that the processor can execute. The millicode and standard system architectures each have there own set of architected registers. However, these registers are dynamically taken from and returned to a common physical register pool under control of a register management system.

Abstract: A computer system has general purpose registers, control registers and access registers for containing information to allow address space capability. A linkage stack uses protected address space to store state information during program call and program return operations. The linkage stack contains information relating to state entries for the saved information and header and trailer entries to point to other linkage stack sections. A control register contains the pointer to the current linkage stack entry and is changed as the program call or return moves through the stack.

Abstract: A thermally optimized piston for use in a liquid cooled module. The thermally optimized piston has three distinctive sections, an upper tapered section, a central cylindrical section, and a lower diverging section. In a preferred embodiment, the thermally optimized piston is provided as part of an improved electronic module. The improved electronic module includes enhanced convective cooling channels disposed between the pistons.

Abstract: An impingement cooled compliant heat sink (CHS) is employed to extract heat from an array of computer chips in an electric module. A variety of embodiments and variations are provided. The most basic implementation is a metal sheet that is brought into contact with chips on a multi-chip module, and acts as a spreader plate for jet impingement immersion cooling with fluorocarbon, liquid nitrogen, or other dielectric liquids. This can increase cooling at a given flow rate by increasing the area for heat transfer. Slots and/or holes in teh sheet located between the chip sites serve to: (1) create flexible joints in the sheet between the chips to permit conformity to neighboring chip sites, (2) allow for clearance of decoupling capacitors and other structures on the substrate between the chips, and (3) permit the dielectric coolant to flow through the plate so that there will be no pressure difference across the CHS.

Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which includes a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the swithc reverses the source and destination field and returns the packet to the sender with an error flag.

Abstract: A thermally optimized piston for use in a liquid cooled module. The thermally optimized piston has three distinctive sections, an upper tapered section, a central cylindrical section, and a lower diverging section. In a preferred embodiment, the thermally optimized piston is provided as part of an improved electronic module. The improved electronic module includes enhanced convective cooling channels disposed between the pistons.

Abstract: A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch reverses the source and destination field and returns the packet to the sender with an error flag.

Abstract: A system and method for instrumenting the execution of instructions in an out-of-sequence execution machine. Instructions tagged with a preselected instruction identification number (IID) are identified. When an instruction having the preselected IID is encountered, information associated with that instruction is saved as the out-of-sequence execution proceeds. If the instruction completes, the information is stored as a single instrumentation entry in a memory array. If the instruction does not complete, the information is disposed of. The process id repeated for each instruction having the preselected IID until the memory array is full. The storage of instruction information in the memory can be further conditioned on the occurrence of a cache miss or other system conditions.

Abstract: An apparatus for converting a multidigit decimal number into a binary number. In a preferred embodiment, the apparatus includes a register for holding the multidigit decimal number; first conversion logic, coupled to the register, for simultaneously converting a first pair of decimal digits in the multidigit decimal number, into a first binary representation and second conversion logic, coupled to said first conversion logic and the register, for simultaneously converting a second pair of decimal digits in the multidigit decimal number and the first binary representation into a second binary representation of a decimal number defined by the first and second pair of decimal digits.

Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: An apparatus and method for removably mounting heat sinks on a chip carrying substrate by simultaneously applying pressure to both the heat sinks and the substrate. Also disclosed is a three dimensional heat sink having a plurality of spatially interconnected holes formed therein. The holes act as extended boiling surfaces which also promote agitation induced by bubble motion.

Abstract: A system and method of cooling which uses both jet impingement and conduction cooling. Conduction cooling is accomplished by placing a cluster of pistons in contact with each chip. The pistons have a rectangular foot at the bottom which contacts the chip. A dielectric coolant, such as liquid nitrogen or fluorocarbon is delivered at the center of each cluster, the fluid flows over the top of the feet, and in the channels between the feet, providing jet enhanced convective cooling at the lower portion of the pistons. Advantageously, the pistons serve as extended surfaces which increase the area over which the forced convection cooling occurs. In a preferred embodiment, microfins protruding from the header sections of each piston further increase the area for heat transfer. In addition, for non-boiling applications, grooves are added to the piston foot surface that contact the chip to insure wetting of the chip-piston interface.

Abstract: An essentially symmetrical ratio decoder which covers all areas in both the positive and negative regions with only a small number of noted exceptions. Multiple boundaries were selected such that the positive and negative regions were symmetrical with only a small number of exceptions. Using these boundaries, an essentially symmetrical, unified ratio decoder was constructed using only about one-half of the integrated circuit real estate of conventional ratio decoder pairs. By decoding the sign bit from the ratio decoder adder, the ratio decoder recognizes the exceptional areas and handles them accordingly.

Abstract: A cold plate and an integrated circuit cooling module embodying a cross-hatch coolant flow distribution scheme. Cross hatch flow distribution is achieved by way of two sets of channels which run perpendicular to each other. The first set of channels is formed on a base plate. The second, perpendicular set is includes a set of inlet channels and a set of interleaved outlet channels formed on a distribution plate. In the preferred embodiment, the base and distribution plates are separated by an interposer plate that has nozzles which cause a liquid coolant to impinge, under pressure, on the floor of the base plate.