Abstract: A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to detect and decode information is provided, wherein the method includes sampling a radio frequency (RF) impulse signal to generate a sample signal and storing the sample signal for a predetermined amount of time.

Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).

Abstract: In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The two least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.

Abstract: The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide antenna diversity to reduce multipath effects is provided. The apparatus may include a primary antenna and a secondary antenna, wherein the antenna gain of the secondary antenna is greater than the antenna gain of the primary antenna. The method may include selectively switching between either a primary antenna or a diversity antenna to receive signals, wherein a gain of the primary antenna is less than a gain of the diversity antenna.

Abstract: A device includes a keyboard and a display. The keyboard allows entry of data into the device, and the display provides an information output. The display has a first position in which the display hides the keyboard, and the display has a second position in which the keyboard is exposed to allow entry of data via the keyboard. The display is visible to the user in both the first position and the second position.

Abstract: According to an embodiment of the invention, the information is transmitted in symbols encoded at a source to a destination. A log likelihood ratio is respectively calculated for each of the encoded symbols. The calculated log likelihood ratios for the information bits are accumulated where the contribution from each of the encoded symbols is accounted for in the accumulating step. Each of the information bits is decoded according to the accumulated log likelihood ratios. An acknowledgment (ACK) is sent to the source for each block of the decoded information bits that passed the error check. A negative acknowledgment (NACK) is sent to the source for each block of the decoded information bits that did not pass the error check. After the source receives the negative acknowledgment (NACK), the encoded symbols are retransmitted to the destination.

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Abstract: Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory device includes a state machine capable of identifying the generic command, writing the specific flash memory commands to a buffer, and sequentially retrieving, interpreting and executing the buffered flash memory commands. The state machine can be configured as a microcontroller executing a state machine algorithm, and can be reprogrammed to correct design errors or to add new functionality to the flash memory device. The state machine algorithm can be stored in the flash memory device, and updated to interpret the same write cycle data in different ways. Accordingly, new functionality can be developed for the state machine long after its silicon has been designed and developed.

Abstract: An improved sense amplifier for RAM arrays is provided which reduces read operation access times, reduces static power consumption and reduces used silicon area. The improved sense amplifier includes an equalizing operation that brings the voltages on the output lines to a midpoint voltage prior to performing a read operation. By providing a midpoint voltage on the output lines, neither output line needs to transition a full rail from Vss to Vcc or vice versa during the amplifying operation, decreasing the amount of time required to read the memory cells.

Abstract: A semiconductor package extractor is provided that extracts a semiconductor package from a socket on a circuit board. The extractor has an outer base and an inner base which are attached via a bolt. Turning the bolt raises or lowers the inner base. The inner base has an inner frame with multiple levers that swing freely inward and outward attached to the inner frame. The levers swing outward to surround the semiconductor package as the inner base is lowered onto the inner base and underlying circuit board. The levers swing inward to securely grip the semiconductor package as the outer base is lowered onto the circuit board. As the bolt is turned, the inner base, gripping the semiconductor package, is raised, removing the semiconductor package from the circuit board.

Abstract: An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write operations in instruction code. In a preferred embodiment, the improved method is implemented in microcode. The method includes detecting multiple suitable write operations prior to the execution, collecting the data elements in a storage unit, and writing the data elements as burst write operations. Write operations that meet specific conditions for quantity of data elements to be written and specific conditions for destination address are suitable for bursting. The improved method can be implemented in existing personal computers, thereby improving system performance without requiring new software applications or a new computer board design.

Abstract: A variable capacitor for integrated circuits used as a decoupling capacitor that operates at both low and high frequencies is disclosed. Based upon a programmable input signal, the decoupling capacitance of the circuit varies within a specific range providing a vehicle for testing decoupling capacitance requirements of new integrated circuits and functions and new silicon processes. The programmable input signal switches a transistor from the saturated region of operation to the unsaturated region of operation, varying the decoupling capacitance of the transistor. By providing circuitry to control the switching of the transistor, the circuit operates at both low and high frequencies, reducing the negative impacts of transistor channel resistance during high frequency operation.