Abstract: In some embodiments, an electronic circuit card includes an edge connector positioned along an edge of the electronic circuit card, wherein the edge connector includes a conductive finger on an outer layer of the electronic circuit card, and a via positioned within the conductive finger, wherein the via electrically connects the conductive finger to another layer of the electronic circuit card. In some embodiments, an electronic circuit card includes an edge connector positioned along an edge of the electronic circuit card, wherein the edge connector includes a conductive finger having a stepped shape. In some embodiments, a connector housing defines a slot, and a plurality of contacts may be disposed inside the housing and positioned along at least one side of the slot, wherein the contacts include a contact surface which is relatively wider at respective interface points on the contacts. Other embodiments are disclosed and claimed.
Abstract: A novel cold plate may include one or more of the following features: relatively narrow channel gaps, two or more flow paths, primarily non-linear flow paths, and/or tapered channel walls.
Abstract: A mechanism is provided at a host node to implement redirection for Class Managers that do not reside on the host node in order to process incoming data messages accordingly in a switched fabric for scalable solutions.
Abstract: A noise injection method for characterizing common clock timing margin (jitter) includes injecting a single tone frequency, varying the amplitude of the injected frequency; measuring the signal produced at various signal amplitudes and analyzing the data obtained from measuring the signal. The obtained measurements may be analyzed using various characterizations such as measured jitter on input, measured jitter transfer, measured jitter tolerance, etc.
Abstract: A method is described that involves forming a product waveform by multiplying a positive signal waveform and negative signal waveform. The positive signal waveform and the negative signal waveform are representative of a logical transition within a differential signal. The crossing point voltage of the logical transition within the differential signal is determined by calculating the square root of a maximum of the product waveform.
Abstract: A platform and a corresponding method for protecting the integrity of data transferred between the user input device and a secure processing unit. In one embodiment, this can be accomplished by establishing a virtual secure path between a device controller of the user input device and the secure processing unit. Thereafter, when sensitive information is input by the user via the user input device, the device controller is placed in a first mode of operation to securely transfer the sensitive information from the user input device to the secure processing unit over the virtual secure path. Additionally, a security indicator is placed in an Active state to indicate to the user that the sensitive information is being securely transferred to the secure processing unit.
Abstract: In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.
Type:
Grant
Filed:
December 30, 1999
Date of Patent:
May 4, 2004
Assignee:
Intel Corporation
Inventors:
William J. Chalmers, Joseph A. Schaefer, Kimberly A. Davis, Don G. Craven, Daniel A. Rich
Abstract: A host system is provided one or more hardware adapters; multiple work queues each configured to send and receive message data via said one or more hardware adapters; multiple completion queues each configured to coalesce completions from multiple work queues belonging to a single hardware adapters; and a completion queue management mechanism configured to check for completions across multiple completion queues in the context of either a single thread or multiple threads of operation.
Type:
Grant
Filed:
March 31, 2000
Date of Patent:
April 6, 2004
Assignee:
Intel Corporation
Inventors:
Jerrie L. Coffman, Mark S. Hefty, Fabian S. Tillier
Abstract: The temperature of a component of a processor power supply that delivers chip core current to a data processor performing in a computer system is sensed. The system has a separate, main power supply from which the processor power supply draws the chip core current. A reduction in, and not a complete stoppage, of the performance of the data processor is requested, in response to the temperature having risen to a predetermined threshold.