Patents Represented by Attorney, Agent or Law Firm Robert A. Rodriquez
  • Patent number: 6583057
    Abstract: A method of forming a semiconductor device by placing a semiconductor substrate in a vacuum chamber and subjecting the semiconductor substrate (20) to a sub-atmospheric pressure, and depositing a layer (40) on the semiconductor substrate while maintaining the sub-atmospheric pressure. Deposition of the layer (40) is carried out by sequentially (i) flowing a first reactant into the vacuum chamber at a first flow rate, (ii) reducing flow of the first reactant into the vacuum chamber to a second flow rate, and (iii) increasing flow of the first reactant into the vacuum chamber to a third flow rate.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: June 24, 2003
    Assignee: Motorola, Inc.
    Inventors: Prasad Alluri, Ramachandran Muralidhar
  • Patent number: 6231743
    Abstract: A substrate (155) is placed into a plating bath (19, 59), a current in the bath is measured, and a film (110) is plated onto the substrate (155). In one embodiment the current is measured using a sensing array (57) positioned within the bath, and the measurement is used to control a plating deposition parameter. In an alternative embodiment the current is measured using the sensing array (57) and a characteristic of the plated film is controlled using a corresponding control array (53) also positioned within the plating bath (59).
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: May 15, 2001
    Assignee: Motorola, Inc.
    Inventor: Gregory S. Etherington
  • Patent number: 6143648
    Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C.sub.2 F.sub.6 and CHF.sub.3 chemistry. The etch chemistry is then changed to an O.sub.2 and CH.sub.3 F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: November 7, 2000
    Assignee: Motorola, Inc.
    Inventors: Robert Arthur Rodriguez, Heather Marie Klesat
  • Patent number: 6136678
    Abstract: A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: October 24, 2000
    Assignee: Motorola, Inc.
    Inventors: Olubunmi Adetutu, James D. Hayden, Chitra Subramanian, Archana Redkar, Anthony Mark Miscione, Mark G. Fernandes