Abstract: Method and apparatus for controlling a processor in a data processing system is described. In an example, the processor is maintained in a halt condition in response to reset information received from the data processing system (e.g., initialization of an integrated circuit having a processor embedded therein). At least one memory resource in communication with the processor is configured. The processor is then released from the halt condition.

Abstract: Method and apparatus for communicating data between a network transceiver and memory circuitry is described. In one example, a transmit peripheral includes a streaming interface configured to receive a communication sequence having data read from the memory circuitry. A receive peripheral includes a streaming interface configured to transmit a communication sequence having data to be written to the memory circuitry. Media access control (MAC) circuitry is configured to transmit the data read from the memory circuitry to the network transceiver, and receive the data to be written to the memory circuitry from the network transceiver.

Abstract: A method of dangling reference detection and garbage collection of VHDL objects within a program includes the steps of providing an Access Value having an Object Reference pointing to an Allocated Object and having and an Access Count pointer pointing to an integer object named Access Count which models a shared access count for the access values. The method sets the Object Reference and the Access Count pointer to null when constructing a new access value and enables an assignment of a negative Access Count to the shared access count when de-allocating a pointer to the Allocated Object. The method also maintains an exact count of a number of pointers pointing to the Allocated Object.

Abstract: Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (504). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced (506) for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced (510, 512) for then instance of the pre-implemented circuit design using the first physical implementation.

Abstract: Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.

Abstract: Composite flip-chip with encased components and method of fabricating the same is described. One aspect of the invention relates to fabricating composite flip-chip packages for integrated circuit dice. Interposing substrates are formed. At least one discrete component is attached to a bottom surface of each of the interposing substrates. A first array of solder balls is placed on the bottom surface of each of the interposing substrates. The interposing substrates are mounted to a carrier strip. The integrated circuit dice are attached to top surfaces of the interposing substrates. The integrated circuit dice and the interposing substrates are encapsulated in molding compound to define flip-chip assemblies.

Abstract: Method and apparatus for digital calibration of an analog-to-digital converter (ADC). One example relates to calibrating an analog-to-digital (A/D) conversion system having an N-bit resolution. The A/D conversion system includes an ADC that generates an output having N most significant bits (MSBs) and M least significant bits (LSBs) (i.e., an N+M bit resolution). An offset calibration circuit is configured to determine an offset in the ADC and to compensate the N+M bit output using the offset to provide an N+M bit offset corrected output. A gain calibration circuit is configured to determine a gain correction factor for the ADC and to compensate the N+M bit offset corrected output using the gain correction factor to provide an N bit offset and gain corrected output.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.

Abstract: Method and apparatus for providing a protection circuit for protecting an integrated circuit design is described. In one example, a sequence generator is defined to produce a pseudorandom sequence of output vectors. A plurality of output vectors is selected from the sequence of output vectors. Bits from the plurality of output vectors are randomly selected to define a terminal vector. Detection logic is generated for detecting the terminal vector. In another example, a protection circuit is defined for asserting a signal after a plurality of clock cycles. At least one lookup table (LUT) is identified in the implemented circuit design having at least one unused input terminal. The signal is coupled to the at least one unused input terminal of the at least one LUT. The protection circuit and the circuit design are then implemented.

Abstract: An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.

Abstract: First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of FIFOs, second storage locations for storing status information for each of the FIFOs, a first port, and a second port. The first port includes a write data terminal for receiving write data and a write address terminal for receiving write addresses. Each of the write addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit. The second port includes a read data terminal for providing read data and a read address terminal for receiving read addresses. Each of the read addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit.

Abstract: Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.

Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: An aspect of the invention relates to a method, apparatus, and computer-readable medium for processing schematic data for an integrated circuit having a boundary scan architecture. A path through cells of the schematic data to generate a hierarchy of cells associated with a boundary scan chain. Each ignore cell in the hierarchy is pruned. Each short cell in the hierarchy is replaced with a direct connection. A shadow net is added to each net of the hierarchy. Each of the cells in the hierarchy is flattened in a bottom-up fashion.

Abstract: Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network. Each of the first FIFO logic and the second FIFO logic is configured for asynchronous serial communication over the interconnection network. Each of the first FIFO logic and the second FIFO logic is further configured to respectively communicate with each of the first logic circuit and the second logic circuit in respective synchronous time domains.

Abstract: Method and apparatus for providing a scheduler select multiplexer is described. In one example, a multiplexer is provided having a plurality of input ports in respective communication with a plurality of queues, an output port, and a select port. A scheduler is provided to execute a scheduling algorithm to periodically generate a schedule comprising a set of entries. Each of the entries comprises at least one bit for controlling the select port of the multiplexer. A memory is provided to store the schedule. For each of a plurality of clock cycles, the select port of the multiplexer is driven with one of the entries such that the multiplexer sends data from one of the plurality of queues to the output port.

Abstract: Automatic antenna diode insertion for integrated circuits is described. In an example, at least a portion of an integrated circuit is defined by a block of standard cells selected from a cell library. A diode circuit is associated with at least one input port of the block of standard cells to form an augmented block. The augmented block is then implemented on a chip to form the integrated circuit. In another example, an integrated circuit is formed by associating a diode circuit with each primary input port of an embedded logic circuit that defines a portion of the integrated circuit. A remaining portion of the integrated circuit is defined by existing logic circuitry. Components of the embedded logic circuit are placed on a chip and conductors are routed connecting the components. The embedded logic circuit is then integrated with the existing circuitry onto the chip.

Abstract: Method and apparatus for implementing a circuit design for at least one integrated circuit on a circuit board is described. In one example, a logical description of the circuit design is obtained. For example, a functional description of the circuit design may be synthesized to produce the logical description. Logical pins in the logical description are assigned to input/output (I/O) elements of the at least one integrated circuit, and the logical description is placed and routed for the at least one integrated circuit, based on external constraint data associated with the circuit board and internal logic constraint data associated with each of the at least one integrated circuit.

Abstract: Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than zero. A set of m memories (204) is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic (206) is provided for coupling each of the processing elements to each of the memories. Control logic (208) is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.

Abstract: Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality of bus interfaces. Arbitration logic is configured for communication with the plurality of ports. The arbitration logic arbitrates access to the memory circuitry among the plurality of bus interfaces on a time shared basis.