Abstract: Disclosed is a digital station apparatus, such as a digital telephone set, capable of being operated in parallel on a subscriber's digital loop (e.g. in an extension mode) without the need to route all the PCM signals to common equipment. Only one of the parallel sets is active at a time; all the others are passive. In the passive state the telephone set receives only, and does not transmit. It monitors its own signal magnitude relative to the signal magnitude produced by the active "extension" on the same digital loop. When its own signal magnitude has satisfied a comparison criterion, then that passive set becomes active and both transmits and receives, while all other sets on the loop are passive.

Abstract: A non-blocking switching network for use in a TDM (time division multiplex) system for switching digital signals carried on incoming buses to outgoing buses (e.g. in a telephone switching office) is disclosed. Each outgoing bus has associated therewith storage devices capable of storing, at least temporarily, all the data received from all the incoming buses. Appropriate control equipment controls which of the incoming channels, stored in the respective storage devices, is applied to the respective outgoing bus. In short, each outgoing bus has associated with itself, dedicated storage devices from which data is applied only to that respective outgoing bus. By this technique, every outgoing bus has access to all the channels on all the incoming buses.

Abstract: A non-blocking switching network for use in a TDM (time division multiplex) system for switching digital signals carried on incoming buses to outgoing buses (e.g. in a telephone switching office) is disclosed. In one embodiment the digital signals, on each pair of incoming buses, are alternately stored in two memory devices. During "even" frames the digital signals from a first incoming bus of the pair are stored in a first memory device and during "odd" frames the digital signals from the first incoming bus of the pair are stored in a second memory device. Similarly, during the "even" frames the digital signals from the second incoming bus of the pair are stored in the second memory device and during the "odd" frames the digital signals from the second incoming bus of the pair are stored in the first memory device.

Abstract: A magnitude comparator circuit is provided for determining the largest binary number, out of a plurality of binary numbers received bit-serially, in parallel. A latch is used to store the results of the comparison and is initialized to an all logic 0 state. The latch has a unique one-bit location corresponding to each number being compared, and a logic 0 stored in the latch indicates that the number corresponding thereto is still in contention (i.e. remains a candidate) for being the largest, and a logic 1 indicates it has been eliminated from contention. As the numbers are received bit by bit (most significant bits first) the bits are applied to gating circuits, one for each number, which invert the bits and store the inverted result in the latch.

Abstract: A digital conference circuit for a digital telephone switching network is provided, connected between a receive TDM (time division multiplex) bus carrying PCM (pulse code modulation) words to the conference circuit and a transmit TDM bus carrying PCM words from the conference circuit. A memory (storage) device stores the PCM words most recently received on the receive TDM bus and decision circuitry determines, for each conferee, which two PCM words, excluding the PCM word originating from that conferee, should be read from the memory device. The two PCM words so read are attenuated in a predetermined fashion, summed, and the resultant PCM sum applied to the transmit TDM bus during an appropriate timeslot. The decision circuit makes its decision based upon the largest average magnitude of each conferee's PCM words, received at the conference circuit, during the previous frames.

Abstract: An interface circuit for interconnection between a central office line and a telephone apparatus (e.g. telephone set, automatic telephone answering machine, etc.) is disclosed. The interface circuit includes a rectifier which allows the interface circuit to be connected across the central office line, in parallel with other interface circuits, without the use of isolation switches.

Abstract: A conversion circuit for use with digital telephone switching equipment for converting pulse amplitude modulation (PAM) signals into pulse code modulated (PCM) signals and for converting PCM signals into PAM signals. When these conversions are done it is desirable to adjust the magnitude of the signals involved to take into account the differing losses in the associated analogue circuitry. The present invention employs digital pads, in the digital portion of the conversion circuit and controlled by a storage register, in order to introduce variations in the signal levels.

Abstract: A fully duplicated memory system for a single central processing unit (CPU) is disclosed. The memory system comprises a primary and a secondary control unit and a primary memory bank and a secondary memory bank. Each memory bank comprises one memory controller and a plurality of memory modules (e.g. six memory modules). Each memory module stores a plurality of binary words in distinct addressable storage locations with a unique address code defining both one distinct addressable storage location in a memory module in the first memory bank and one distinct addressable storage location in a memory module in the second memory bank. A random access memory (RAM) stores an indication of the read and write status of each memory module in both the first and second memory banks. One of the control units, responsive to both the CPU and the RAM determines which memory bank (primary or secondary) is accessed in response to a read or a write command from the CPU addressed to the memory banks.

Abstract: A circuit for reducing the effects of polarization crosstalk occurring on a first RF signal due to a second RF signal, wherein the first and the second RF signals are two approximately orthogonally polarized RF signals having essentially the same frequency. The circuit comprises a first antenna and a first signal path (including RF and IF sections) for the first RF signal and a second antenna and a second signal path (including RF and IF sections) for the second RF signals. A first coupler diverts a portion of the signal on the second signal path into a first network comprising the series combination of a variable attenuator and a variable phase shifter. A summing circuit sums both the signal on the first signal path and the signal output from the first network with the result that the undesired signal on the first signal path is reduced. A logic circuit, responsive to the magnitude of one of the RF signals, controls the first network according to a predetermined relationship.

Abstract: A static, solid-state originating register for use with an electromechanical telephone cross-bar switching system (e.g. an NE-5* switching system by Northern Telecom) is disclosed. The static, solid-state originating register comprises a plurality of static, solid-state scan networks responsive to an equal plurality of scan points, in a one-to-one relationship, for monitoring the status of the scan points. Also included are a plurality of static, solid-state signal distributor networks for activating associated equipment in the switching system. A microprocessor is employed for controlling the operation of the scan networks and the signal distributor networks. An isolator device is used for interfacing the microprocessor with both the scan networks and the signal distributor networks.

Abstract: An alternate routing scheme for a telephone system wherein a plurality of switching offices are grouped into a cluster, with each switching office in the cluster having direct trunk lines to all the other switching offices in its cluster. This allows each switching office in the cluster to serve the dual function both of an originating (or terminating) office and of a tandeming office for its own cluster. Suitable equipment monitors the busy status of all the switching offices in the cluster, and determines a most likely alternate routing scheme for each switching office. The alternate routing scheme for each particular switching office is stored at that particular office and is periodically updated, by suitable equipment, so as to account for changes in the busy status of the other switching offices and trunk lines in the cluster.

Abstract: An auxiliary winding is provided on a ferroresonant voltage regulating transformer. The transformer is controlled in such a manner that, during start-up of a load connected to the transformer, the auxiliary winding provides all the current for the load, and after the initial start-up period of the load, the auxiliary winding is disconnected from the load and the normal secondary winding of the ferroresonant transformer supplies all the current to the load. It should be noted that the auxiliary winding is constructed so that (in theory) all the flux from the auxiliary winding is linked with the primary winding, and all the flux from the primary winding is linked with the auxiliary winding.

Abstract: An improved latching lever for use with a printed circuit board (PCB). The latching mechanism comprises a hooked portion flexibly connected to the body portion of the latching lever, an actuating member solidly connected to the hooked portion for moving the hooked portion relative to the body portion, and a stop portion, solidly connected to the body portion for limiting the movement of the actuating member. A stud carried by the PCB is engaged by the hooked portion of the lever to enable the lever to latch. Moving the actuating member to touch the stop portion disengages the hooked portion from the stud, thereby unlatching the lever, and leaving the lever free to pivot about its pivot point.

Abstract: The subject invention is a sample-and-hold circuit that provides current gain and that is suitable for construction according to LSI (large scale integration) techniques. The circuit incorporates a bipolar transistor biased on (in the "sample" mode) to a predetermined quiescent state. A capacitor is connected across the output of the circuit (i.e. across the output of the bipolar transistor) to be charged to a certain voltage by the bipolar transistor and to store this voltage when the sample-and-hold circuit is in the "hold" mode of operation. IGFETs (insulated gate field effect transistors) are employed to bias the bipolar transistor and to switch the circuit from one mode of operation to the other.

Abstract: A digital conference circuit for a digital telephone switching network is provided, connected between a receive TDM (time division multiplex) bus carrying PCM (pulse code modulation) words from the conferees to the conference circuit and a transmit TDM bus carrying PCM words from the conference circuit to the conferees. For a conference involving N conferees, N-1 shift registers serially interconnected are employed. As each PCM word, in a distinct time slot on the receive TDM bus, reaches the conference circuit it is entered into the first shift register in the series. The PCM words already stored in the shift registers are "shifted" along the series connection of shift registers by one register each time a new PCM word is entered in the first register, with the PCM word previously stored in the final shift register simply being "lost.

Abstract: A pulse width modulation (PWM) converter circuit for transforming a first DC voltage into a secondvoltage (AC or DC), wherein the magnitude of the second voltage is regulated by the converter circuit. The converter circuit comprises a clock circuit, a master pulse width modulator (PWM) circuit and n slave pulse width modulator (PWM) circuits. The clock circuit provides a symmetrical train of rectangular pulses on each of n+1 conductors, wherein only one pulse occurs on any one of the conductors at one time. The master PWM means is responsive both to the train of pulses on one of the n+1 conductors and to a feedback signal indicative of the magnitude of the second voltage; the master PWM means controls the flow of current, due to the first DC voltage, through a portion of a transformer primary winding.

Abstract: A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produced. The twenty-four bit product can be coded as an unsigned seven-bit binary number (.mu.-255 code) as follows. The number 33.times.2.sup.11 in binary form is added to the linear product to form an augmented product. The number of leading zeroes in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are used for the four least significant bit positions of the coded product.

Abstract: In a push-pull inverter (including a transformer) for changing direct current into alternating current, a circuit is disclosed for starting the inverter in which the first pulse of a rectangular pulse train applied to the transformer has a duration of one half that of the subsequent pulses. This aids in reducing the initial magnitude of the flux excursion in the transformer core.

Abstract: A coaxial transformer is employed to provide impedance matching for the input of a bipolar transistor operated in the VHF frequency range. The coaxial transformer comprises a first winding wound around a ferrite toroidal core. The second winding has a single turn and consists of a metal enclosure substantially surrounding the first winding. One end of the first winding is connected to the base of the transistor and the other end of the first winding is connected to ground. One end of the second winding is connected to the emitter of the transistor and the other end of the second winding is connected to ground.