Abstract: Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed.

Abstract: A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

Abstract: In a chemical-mechanical polishing (CMP) process, semiconductor substrates are rotated against a polishing pad in order to planarize substrate layers. The condition of the polishing pad directly affects the polishing rate of material removal and uniformity of removal from the semiconductor wafer. Conditioning of the polishing pad surface with an abrasive improves polishing uniformity and rates, however, it has the detrimental affect of removing a quantity of pad material. A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters.