Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.

Abstract: A liquid crystal display having an injection hole post structures compatible with liquid crystal are formed in an area near an injection hole to prevent pollutants seeped from an end-sealing material from penetrating into a display area, thereby suppressing the occurrence of picture quality trouble which easily occurs in the display area. The liquid crystal display includes a first substrate 11 and a second substrate 12 which are disposed with a predetermined gap therebetween, in which liquid crystal is sealed in the gap.

Abstract: The present invention provides a method and apparatus to browse the Web without using a web browser. The application server in a transmitting unit converts a web page transmitted from the Internet into video data and provides links to the video data on the basis of the links provided to the web page. In the video server of the transmitting unit, the video data transmitted from the server is compressed by the MPEG2 encoders, and sent with information about the links provided to the video data. A ‘Set-Top Box’, of the receiving terminal outputs the received video data to a display, and establishes an association between the links provided to the video data and a position of a cursor displayed on the screen of the display.

Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.

Abstract: In accordance with the present invention, there is provided a method for sharing a secret value x among n participating network devices via an asynchronous network. The n participating network devices comprises t faulty devices and k sub-devices capable of reconstructing the secret value x, wherein t<n/3 and k<n. The secret value x being provided by a distributor.

Abstract: A hierarchical gateway system for use in a message delivery system is disclosed, in which each tier of gateways in the hierarchy includes means for transforming incoming messages in a manner required by downstream end-user devices. The hierarchical gateway system has the advantage of being scalable and extensible while avoiding transmission bottlenecks as the number of end-user device types, and their differing system requirements, increase. The invention is operable in the context of a notification server architecture, as well as the Web.

Abstract: A novel asymmetric filter membrane, and process for making is disclosed in several exemplary versions. The membrane structure is physically robust and suitable for use in a wide variety of applications. The support membrane is may be comprised of material such as a porous silicon or a silicon oxide, and the separation membrane may be comprised of material such as a polymer, zeolite film, or silicon oxide. The process relies on steps adapted from the microelectronics industry.

Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Abstract: The invention relates to a method for creating a pattern on a substrate comprising a first alignment structure, using an elastomeric stamp comprising a patterning structure and a second alignment structure. The method comprises a moving step for moving the elastomeric stamp towards the substrate, and a deformation step for deforming the patterning structure with a tensile or compressive force generated by cooperation of the first alignment structure and the second alignment structure.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas.

Abstract: A microsystem switch (1, 20, 25, 30, 33) has a support (2) defining a recess (3), and a flexible bridge (6) is mounted on the support (2) bridging the recess (3). The bridge (6) is shaped so as to hold selectively a concave stable state, in which the bridge bulges into the recess (3), and a convex stable state in which the bridge bulges out of the recess (3). The switch includes an actuator (8, 9; 26, 27) for effecting flexing of the bridge (6) between the stable states, and a switching element (7, 31, 34) is mounted on the bridge (6) such that movement of the bridge between the stable states moves the switching element between an on position and an off position. According to another design, a microsystem switch (40, 55) has a support (41) defining a recess (42), and an elongate torsion member (44) is mounted on the support (41) bridging the recess (42). A flexible bridge (43, 56) is mounted on the support (41) bridging the recess (42) in a direction substantially perpendicular to the torsion member (44).

Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: A matrix addressed display device having a cathode means and grid electrode means comprising an orthogonal array of parallel row conductors and parallel column conductors in which means are providing for selectively applying cut-off and gain correction information to the row conductors and the column conductors. The cut-off and gain correction information may be applied so as to affect all of the display area equally and correct for warm up drift, or it may be applied so as to correct for the effect of a discrete number of hot cathode filaments being used or it may be applied on a pixel by pixel basis.

Abstract: A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.

Abstract: A magnetoresistive sensor includes a substrate and a layer of ferromagnetic material formed over the substrate. A plurality of nonmagnetic regions is formed within the layer of ferromagnetic material. Magnetic flux paths form around each one of the plurality of nonmagnetic regions when the layers of ferromagnetic material is not in a magnetic field. The flux paths are contained completely with the layer of ferromagnetic material and do not penetrate into the plurality of nonmagnetic regions. The sensor also provides for detecting a change in resistance through the layer of ferromagnetic material as a function of a magnetic field applied to the layer of ferromagnetic material.

Abstract: A microelectronic device includes a gate layer adapted to receive an input voltage. An insulating layer is formed on the gate layer, and a conductive channel layer is formed on the insulating layer and carries current between a source and a drain. The conductive channel layer is adapted to provide a dual channel. The dual channel includes both a p-channel and an n-channel wherein one of the p-channel and the n-channel are selectively enabled responsive to the input voltage polarity. A method for forming the device and applications are also disclosed and claimed.

Abstract: A method for fabricating a display device patterns a conductive layer on a display substrate and forms pixel electrodes on the display substrate. A plate is employed for carrying separately fabricated active devices to the display substrate. The separately fabricated devices are connected to the conductive layers and the pixel electrode.