Abstract: An insulated-gate semiconductor device includes an IGFET with channel, base, drift and drain regions, and further includes source and drain electrodes attached to at least the base region and to the drain region, repectively. The device further includes a carrier injection region which adjoins the IGFET drift region and forms a P-N junction therewith. Biasing structure connected to the carrier injection region and effective during the on-state of the device is provided for forward biasing the P-N junction by an amount sufficient to induce injection of carriers from the carrier injection region, across the P-N junction, and into the IGFET drift region. As a consequence, the on-resistance of the device is markedly reduced.

Abstract: An improved method and apparatus for reducing edge field enhancement in semiconductor devices such as metal-insulator-semiconductor devices is disclosed. The method comprises the step of biasing a buffer gate which overlies an insulation layer and an area of a substrate in which it is desired to reduce the edge field enhancement at a voltage exceeding the flatband voltage so that a buffered zone is created in the substrate. The apparatus consists of a substrate, a plurality of insulating layers overlying the substrate, at least one gate electrode formed on one of the insulating layers and a buffer gate formed on a second of the insulating layers. When the gate electrode is biased so that a potential well is formed in the substrate, the buffer gate is simultaneously biased so that a buffered zone which adjoins the potential well is formed.

Abstract: An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.

Abstract: A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operation, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.

Abstract: An enhanced manufacturing yield of a high resolution, high accuracy information conversion device, such as a liquid crystal display, is attained through incorporation into the device of auxiliary address lines. Such auxiliary address lines are used to provide electrical communication with portions of main address lines that, due to the presence of electrical open circuits, would otherwise be electrically isolated. Each auxiliary address line crosses over multiple main address lines and can be electrically shorted to any such main address line to provide electrical communication therewith. The ratio of auxiliary address lines to main address lines is accordingly low, such as 1:10 or less, for example.

Abstract: A reflector antenna system with reduced blockage effects is provided by placing a compensating reflector between the surface of the main curved reflector and its primary feed to intercept illuminating radiation which would otherwise be blocked by the feed. The compensating reflector reflects the intercepted radiation with a beam pattern which is essentially identical to the substractive blockage pattern. The compensating reflector is spaced from the main reflecting surface to place its beam pattern in phase opposition to the blockage pattern to cancel common components from the blockage pattern.

Abstract: An improved automatic placement process for placing logic cells in a universal array. Unused basic units are assigned to rows to reduce the congestion of the wiring in high congestion regions of a universal array. These assigned unused basic units are allocated among rows in a pyramidal manner. Those unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion. During a pair exchange portion of the placement process, quality criteria used for deciding whether to exchange two logic cells on different rows include skipped rows in a node, y-span of a node, minimizing the number of logic cells in excess of two in a node on a row, making a longest row shorter and making longer a shortest row or one which is within a tolerance of being a shortest row.

Abstract: A corrosion resistant resilient electrically conductive gasket is comprised of a metal-containing conductive elastomer which has had any exposed metal coated with a protective conductive coating. The metal may be silver and the coating may be tin-lead solder applied by immersing the gasket into a molten solder bath.

Abstract: An enclosure for electronic systems provides substantially total RF isolation of separate segments of a system except for the transmission of desired signals between different segments, even though the various segments are fabricated on a common circuit board. A special multilayer circuit board configuration makes this isolation feasible. Buffer circuits connected to drive signals on and receive signals from conductors which extend between isolated compartments prevent communication of stray signals along those conductors.

Abstract: A continuously variable phase shifter for the phase range from 0.degree. to 90.degree., switchable phase shifters switchable between 0.degree. and 90.degree. and a continuously variable phase shifter for the phase shift range of 0.degree. to 360.degree. are disclosed. Each of the phase shifters relies on dual gate FET devices to provide the required phase shift in a compact structure while providing sufficient gain to avoid signal losses through the phase shifter. The transmission phase shift through a dual gate FET device is controlled by the DC bias on its second gate and by the type of reactive termination on that gate. A capacitive termination provides a transmission phase shift which is substantially independent of bias while an inductive termination provides a transmission phase shift which varies substantially linearly with bias voltage over a substantial range of bias voltage.

Abstract: A redundancy switching system which provides four reserve devices is disclosed which is suitable for use with from eight to twelve channels. The switches in the input switching network of this redundancy system are connected in first and second sections. Each section includes a ring of switches and two switches connected as appendages to the ring. Only as many switches are needed to control the input connection to the redundant devices as there are redundant devices. A similar number of switches are needed to control the output connection of the active devices.

Abstract: A routing process for automatic computer aided routing of customizing conductors in a universal array which has a single customizing conductive layer is improved by executing a pathfinding routing process for conductors which connect pins on the same row before routing other conductor types. Routing of conductors which connect a pin on the side surface to a pin in the basic unit row region is improved by initially restricting permissible routes to be within a set of three contiguous rectangles. Routing opportunities for potentially failed conductors are increased by allowing customizing conductors to extend parallel to the length of the basic unit rows in the region between adjacent tunnel ranks in the final routing step. An improved custom IC results.The conductor number of the shortest and the longest conductor in each class is stored separately from the routing grid matrix so that these numbers can be directly retrieved as needed.

Abstract: A four-port folded interdigitated coupler has two short conductive strips and three full length conductive strips disposed between the short strips. The full length strips are 1/4 wavelength long at a design frequency. The sum of the lengths of the short strips is 1/4 wavelength at that design frequency. The ends of the short strips remote from the ports are connected together and to the center one of the three full length strips by conductive jumpers. In one embodiment the two full length strips which are not connected to the short strips are connected by a conductive jumper at substantially the same longitudinal position as the jumpers which connect the ends of the two short strips. In this embodiment, the two short strips may have equal lengths or they may have unequal lengths. When their lengths are unequal, their jumpers and the associated jumper between the two outer full length strips are positioned off-center with respect to the longitudinal length of the full length strips.

Abstract: A waveguide or waveguide phase shifter is terminated with a short circuit provided by a rigid conductive block which is sized to be a close tolerance fit within the waveguide. The block has grooves in its faces adjacent to the waveguide walls. The walls of the waveguide are deformed to project into these grooves to permanently secure the waveguide to the block.

Abstract: An IC having closely packed rows of cells enables both regular structures (register stacks and memories) and random logic structures to be efficiently fabricated from it. Circuits having more parallel-to-the-length-of-the-rows interconnecting wiring than regular structures have wiring corridors over inactive rows of cells whose cells are not connected into the circuit. A grid power bus structure smooths power flow with a minimum of active device loss by hyphenating "large" cells across the cell-row-crossing conductors.

Abstract: A switched-line type phase shifter employs a reference, uniform transmission line and a coupled exponential transmission line. The coupled exponential line network provides a different phase shift but provides a phase shift versus frequency characteristic that over a wide frequency band matches the reference line.

Abstract: A system for adjusting the antenna matching network of a radio system in the presence of an interfering signal in the matching network being adjusted comprises a loop from which the interfering signal is cancelled by an adaptive interference cancellation (AIC) system. The AIC system receives an interference sensor signal having the frequency of the interfering signal. Means responsive to the interference sensor signal and phase and amplitude control signals provides a modified interference sensor signal having a phase and amplitude determined by the control signals. This modified interference sensor signal is combined with a mismatch signal which is derived from the signal in the matching network to produce a modified mismatch signal.

Abstract: High gate count integrated circuits (ICs) are designed in a heirarchical manner. In a first pass through a computer design system basic cells are composed to form one-level-up building block cells. In a second pass through the same computer design system the one-level-up building block cells are used as "basic" cells and composed to form a two-level-up structure which may be a building block cell or a chip.

Abstract: A system for determining the delay between first and second signals includes apparatus for characterizing each signal and apparatus responsive to corresponding portions of the first and second characterizations for providing an estimate of the delay of the second signal relative to the first. In a preferred embodiment the characterizer dissects the signal into a plurality of separate components each having a different frequency. A cross-characterizer determines the time delay between corresponding components of the two characterizations and derives a weight for each determined delay. A cross-characterization combiner forms a weighted sum of the determined component delays which becomes the discriminated delay between the two signals.

Abstract: Two microstrip transmission line substrates are mounted face-to-face at a fixed separation determined by mating connector halves which provide microstrip to coaxial transmission line transitions. Each connector half includes a body portion, a stand-off portion and a coaxial connector portion.