Abstract: An apparatus for and method of predefining a series of messages between a client application and a server application which needed to be transferred and honored in sequence to perform a compound service request. The sequence of messages is predefined through the use of an Action Control List, whereby the event handler defines the messages to the administrative object.

Abstract: An apparatus for and method of utilizing an Internet terminal coupled to the world wide web to access a legacy data base management system having a dialog-based request format to prepare, modify, and execute stored procedures. The user request is passed to the legacy data base management system via the Internet. The command type is determined whereby list, parameter, column, and execute commands are defined. In response to the user request, the scripted procedure is accessed, prepared, modified, or executed, as appropriate. Invalid and/or undefined requests result in an error response. Valid and defined requests result in performance of the requested command and transfer of an appropriate response to the user terminal.

Abstract: A computer system comprises an operating system that provides a file system for storage of objects. A compile manager creates a repository within the file system in response to a compilation request. A directory stores file names previously generated by the compile manager during a compilation process. In response to the request for compilation of one of the objects, the compile manager automatically creates the repository within the file system with a unique file name based at least in part on an object name associated with the requested object and a number of file names within the directory that match at least a portion of the object name. Each filename may include one or more characters from a filename portion of the name of an object and one or more characters from a version portion of the name of the object.

Abstract: Techniques are described of using votes of third-party components to select a master processor from a plurality of redundant processors. A master processor and a standby processor maintain communications with one another. If communication between the master processor and the standby processor fails, the processors may poll a set of registered voters to determine which of the processors is to be the master processor. In this way, the processors may determine which of the processors is to be master without the use of a shared indicator to specify which of the processors is to be the master processor.

Abstract: Techniques are described for mapping an emulated SSL implementation to, for example, OpenSSL.

Abstract: Supporting limited address mode memory access involves receiving a write request from the processor targeted to a first predetermined address. A data portion of the write request includes a target address of the system memory. In response to determining the write request is targeted to the first predetermined address, the target address is sent via a system interface to be stored in a configuration register of the processor director. A memory access request targeted to a second predetermined address is received from the processor. In response to determining the memory access request is targeted to the second predetermined address, the target address is retrieved from the configuration register of the processor director. The memory access is serviced using the target address retrieved from the configuration register.

Abstract: This application generally describes techniques for dynamically updating trusted certificates and CRLs, generally referred to herein as certificate information. That is, techniques are described for updating trusted certificates and CRLs without terminating existing communication sessions. An exemplary method includes the steps of receiving an initial configuration that includes a trusted certificate authority, receiving certificate information that includes a certificate revocation list (CRL) and a first certificate from the trusted certificate authority, storing the certificate information in the configuration, initiating a communication session for an application, receiving an update to the certificate information, and updating the configuration to reflect the update to the certificate information without terminating the communication session.

Abstract: Disclosure of approaches for processing database transactions against a database. In one approach, a first transaction is received that specifies an operation for changing state of a first record stored in a first database page. In processing the operation, the state of the record is changed, and information is stored in a companion page. The information includes a transaction identifier, data describing the specified operation, a page identifier of the first page, a before look and an after look of the first record for an update operation, and an after look of the first record for an insert operation. In response to a commit of the first transaction, a process determines whether a second transaction, that specifies a change in state for a second stored in the first page, is in-process. In response to determining that the second transaction is in process, the companion page is stored in an audit trail.

Abstract: A method and a system for converting logical aspects of a common warehouse model (CWM) to corresponding design items for a relational database by processing in a hierarchical manner the logical aspects and creating the corresponding design items. The logical aspects comprise entity-relationship (ER) libraries. The ER libraries comprise ER models. The corresponding design items comprise design libraries. The design libraries comprise design models.

Abstract: Various approaches for processing a B+ tree data structure are described. In one approach, in a first transaction a first insert operation to a first data page of a first index page in the B+ tree data structure is detected, and then it is determined whether performing the first insert operation would block a second insert operation in a second transaction concurrent with the first transaction. At least one empty second data page is created in response to determining that the second insert operation would be blocked by the first insert operation. The B+ tree data structure is updated to include the at least one second data page in the B+ tree data structure, and the updated index pages and second data page are committed to retentive storage. Thereafter, the first insert can be completed.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: The current invention provides a mechanism for detecting and recovering from glitches on data strobes. In one embodiment, data is captured from an interlace by a receiver using at least one data strobe that is provided by the transmitter along with the data. A write address counter that is clocked by the data strobe is used to count the active edges of the data strobe. A read address counter that is periodically synchronized with the write address counter, but that is clocked by an internal clock of the receiver, is used to count units of data being received from the interface. Periodically, the contents of the read and write counters are compared. If the contents are not the same, a glitch has occurred on the data strobe. The glitch is recoverable if it occurs on, or after, a last strobe edge of a data transfer.

Abstract: A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.

Abstract: Various approaches for processing a B+tree data structure of a database are disclosed. In one approach a method determines a pattern of multi-column key values. In response to an insert transaction into the database that requires a new index page and before performing the insert transaction, the method generates a plurality of new multi-column key values based on the pattern and stores one or more of the plurality of multi-column key values in one or more new index pages. Before performing the insert, the method further commits to retentive storage of the one or more new index pages and new data pages as linked to the B+tree. After committing the one or more new index pages and new data pages, the method then proceeds to processes and commits the insert transaction.

Abstract: A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.

Abstract: In general, techniques for secure communicating over a virtual IPMB of a mainframe computing system are described herein. More specifically, the mainframe computing system comprises a plurality of independent computing cells communicatively coupled together by a network interconnect and that form a plurality of partitions. Each partition is a logical association of one or more of the cells to define a single execution environment. Each cell further executes a virtual intelligent platform management interface (IPMI) protocol to define and configure a respective logical intelligent platform management bus (IPMB) for each of the partitions. Each of the IPMBs logically interconnects with each of the other cells included within the same partition, and each is defined for communication of IMPI messages over the network interconnect. The cells securely communicate the IPMI messages between each of the one or more other cells of each partition via the respective logical IPMB of each partition.

Abstract: A telephony-based messaging system application is built for use by a particular customer. The application is stored on a computer readable medium and includes a set of modules, where each module comprises call flows, code and a Customization List. The Customization List includes one or more tables each having a list of names and a modifiable list of corresponding DTMF signal identifiers. With this architecture, the particular customer is permitted to change the mapping between caller-entered DTMF signals and the corresponding actions taken by the messaging system by modifying the list of DTMF signal identifiers, i.e., without modifying the call flows or code.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.