Abstract: A tunable filter (100) is provided including a first resonator (110) and a second resonator (120). The bandwidth of the tunable filter is maintained constant by providing purely inductive coupling (114) between the first and the second resonators (110 and 120). The first and the second resonators (110 and 120) include tuning elements (108-109 and 118-119) which are second coupled to each other by means of a capacitor (130) to improve image rejection performance of the tunable filter (100).

Abstract: A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique.

Abstract: The functions of two virtual operating systems (e. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A computer having slots for attachment of expansion adapters contains means enabling the system formed by the computer and attached adapters to reconfigure automatically, when an adapter is either inserted into an empty slot or removed from an occupied slot, while the system is fully powered and in an application running state. Insertion of an adapter into an empty slot is detected by an adapter detection mechanism. The mechanism signals a programmed resource manager element in the computer, via an interrupt or the like, and the resource manager then sequences the computer and inserted adapter through a series of mechanical and electrical reconfiguring operations. In these operations, the adapter is physically locked into place relative to the slot, supplied with power from a source in the computer, and signal conduction paths through the slot are activated.

Abstract: A multiprocessor computer includes a planar board and a processor card mounted on the planar board. An interrupt controller is mounted on the planar board and has a plurality of interrupt input lines for receiving interrupt requests from a plurality of interrupting devices. The interrupt controller also has an output line that transmits an interrupt to the processor card. The processor card includes an interrupt director having a plurality of interrupt request lines respectively connected to interrupt request pins of the different processors. The director is also connected to the output line coming from the interrupt controller. In response to receiving an interrupt request from the interrupt controller, the director performs an interrupt acknowledge cycle and transmits an interrupt request, on only one of the interrupt request lines, to a specific processor predetermined by the director. The specific processor then reads an interrupt vector from the director.

Abstract: A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.

Abstract: A personal computer system compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus and a direct access storage device electrically responsive to the data bus, the direct access storage device storing a second portion of operating system microcode. The non-volatile memory stores a first portion of operating system microcode and the direct access storage device stores a second portion of operating system microcode. The second portion of operating system microcode includes a boot program. The first portion of operating system microcode verifies the integrity of the boot program prior to loading the boot program into the volatile memory.

Abstract: A battery unit charger system is provided which includes a charger (110) for supplying charge current and a battery (120) having a memory (122) for storing battery-related information. The charger (110) includes a controller which exchanges the battery-related information with the memory (122) and in response thereto, controls overall operation of the charger (120). The battery (120) includes a common battery port (126) for selectively receiving charge current and for exchanging data with the charger (120). The controller cuts off the supply of charge current when data is being exchanged with the memory through the common port (126).

Abstract: A method for adjusting elements of a graphical user interface operating system is disclosed. The method includes providing the operating system with a plurality of palette managers; each palette manager includes a plurality of element values. The palette managers are represented on a display device by icons, are accessible via windows and are responsive to a pointer. One of the palette managers is activated via the pointer to provide an activated palette manager window. One of the values of the activated palette manager window is selected via the pointer. The selected value is dragged to an element to be updated and dropped on that element. Dropping the selected value causes the element to be updated to correspond to the selected value.

Abstract: A portable communication device (10) is controlled by voice recognition circuitry (20) remote from the portable communication device. The portable communication device includes apparatus for producing and transmitting a parametric representation of voice commands. The remote circuitry (which could possibly be a base station, a mobile repeater, or simply a dedicated box, separate from the portable) produces control signals, responsive to the parametric representation of voice commands, for controlling the portable communication device.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: A sealed microphone assembly is disclosed including a microphone (120), a microphone housing (110) having a cavity (116) being resonant at an audio frequency range, and a sealing membrane (130). The sealing membrane 130 covers the cavity 116, thereby making the microphone assembly (100) fully sealed. The attenuation caused by sealing the microphone assembly (100) is compensated by the resonant characteristic of the cavity (116). The cavity (116) also includes one or more apertures (112) for creating a bandpass response.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques, The S/370 is limit checked prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: Supply of energy to a radio device (220) as provided by a battery pack (210) is remotely controlled by coupling a transistor switch (213) between an energy source (212) within the battery pack (210) and battery terminals (222 and 224). The transistor switch (213) is controlled by a control signal (238) which is applied to the battery (210) through a control terminal (217) disposed on the battery.

Abstract: In a CDMA communication system (100) capable of communicating between a receiver (10) and a transmitter (20)direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver chip timing and transmitter chip timing. Transmitter (10) transmits a training bit sequence (31) coded with a spreading chip sequence. The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). The representation of the despreading chip sequence is represented by tap coefficient potentials of the equalizer (400). Receiver chip timing offset is determined based on the tap coefficient potentials.

Abstract: A data processing system adapted to perform a plurality of interleaved data processing functions (2, 4, 6), characterised in that each data processing function (2, 4, 6) stores self-diagnostic trace data in a memory (16) shared between the data processing functions (2,4,6) and the data processing system performs a trace function (8) which reads the trace data from the shared memory (16) and correlates the trace data into a single output. The disclosed system provides a trace facility in which a single correlated trace output is produced from the trace messages produced by all the different data processing functions (2, 4, 6). A single correlated output enables errors involving the interaction of two or more data processing functions (2, 4, 6) to be more easily identified.

Abstract: In an adaptive CDMA receiver (20), a DS-SS received signal and a reference signal are equalized by minimizing the error between them the received signal includes a desired DS-SS communication signal comprising binary bits coded with spreading chip sequences. The received signal is sampled at a chip rate to produce sampled received signals which are correlated with each other. The received samples are de-correlated by employing an orthogonal transformation algorithm to provide de-correlated elements corresponding to the received samples. The equalization process is accelerated by minimizing the error based on the de-correlated elements.

Abstract: A personal computer has a memory system including a write-through cache which is accessible by more than one device. A snoop mechanism includes logic that monitors bus master control signals to determine if a new memory write cycle has been started before a current snoop cycle has finished. If a new cycle has been started, then a corresponding snoop cycle occurs which overlaps the new memory cycle and is pipelined with the previous snoop cycle so that the snooping mechanism does not fall behind the memory write cycles.