Abstract: A Surface Wave Acoustic (SAW) is constructed with hyperbolically curved electrode fingers. The transducers consist of relatively narrower inner electrode fingers and relatively wider outer electrode fingers, and may also be divided into a plurality of tracks with each of the tracks being subdivided into a plurality of subtransducer elements which are capacitively coupled in electrical series.

Abstract: Data bits are decoded from a composite signal that is formed by coding multiple bit sequences with respective spreading codes, and transmitting the coded bit sequences simultaneously and asynchronously over a single channel in which the bit sequences are added. This decoding involves a metric in combination with a repetitive decision process which is only linearly dependent on the number of bit sequences in the composite signal.

Abstract: A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.

Abstract: Manchester level coded data is converted to NRZ by two gated delay line oscillators responsive to differential Manchester signals for providing a single gated pulse in response to consecutive data cells conveying the same data and for providing two pulses in response to a data change. A decoder circuit responds to the two pulse condition by toggling a data flip-flop that provides the NRZ data. The flip-flop also controls gates responsive to the two oscillators for selecting between the two oscillator signals to provide the NRZ clock. When the system bus ceases data transmission, three or more oscillator pulses are generated, the detection of which is utilized to preset the data flip-flop.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: A novel maximum likeihood decoder for the Golay (24,12) code is provided. Instead of decoding the received dimensional vector (X) is a systolic array, the vector is mapped into a (24,5) subcode with an index 128 which is easily decoded. The decoder employs a plurality of precomputational circuits cooperating with a similar plurality of inner product circuits which compute the 128 inner product values and select the maximum inner product value from each inner product circuit. The maximum inner product value from each circuit is loaded into a select logic circuit for selecting the maximum inner product value and its corresponding code word closest to the received vector (X).

Abstract: A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines of a pair, and a base coupled through a diode means to the second bit line. A second bipolar transistor has its collector-emitter path coupled to the second bit line and its base coupled through a second diode to the first bit line. The collectors of both of the bipolar transistors are coupled to provide an output signal. Resistors are coupled to a pulse source and to both of the bases of the bipolar transistors. A current sink is coupled to both of the select bit lines. The diode means are connected so as to be forward biased when the base-emitter junction of the transistor to which the diode means is coupled is also forward biased.

Abstract: A non-reprogrammable ROM holding microinstruction words cooperates with a Content Addressable Memory made of a TAG Memory and Data Memory. Portions of the locations in the TAG Memory have the same address as certain locations in the ROM so that when these selected addresses occur, a multiplexer will select the updated data from the Data Memory rather that from the ROM. The entire system is placed on one chip and provides great spatial surface savings over that which would be required if only a Static RAM were used for a control storage unit to hold the microinstruction words.

Abstract: A machine for bonding leads from a chip to a substrate having top and bottom surfaces that are non-coplanar is comprised of a carrier for the substrate which includes a frame having a set of stops that terminate in a single plane and which are arranged in a pattern with a central opening. Also included in the carrier is a forcing mechanism which pushes on the bottom surface of the substrate such that the top surface of the substrate is pinned directly against all of the stops simultaneously and a portion of that top surface is exposed through the opening. This causes the exposed portion of the substrate's top surface to be aligned with the plane of the stops regardless of the degree of non-coplanarity that exists between the substrate's top and bottom surfaces.

Abstract: A leak in an enclosure of an integrated circuit package is detected by the steps of: filling the enclosure with a first gas at the time the enclosure is sealed; subsequently enveloping the integrated circuit package with a second gas that is different than the first gas; holding the second gas at a constant pressure over a certain time period; and sensing a surface of the enclosure, during the above steps, for the presence of microscopic deflections. If the enclosure has a gross leak, no deflection will occur when the package is initially enveloped with the second gas. If the package has a minor leak, a deflection will occur when the package is initially enveloped with the second gas, and the amount of the deflection will decrease during the holding time period.

Abstract: The present invention provides a novel burst erasing automatic gain control circuit which includes the basic elements of an automatic gain control circuit and further includes in the loop control circuit, slow response wideband filter means, and a hard limiter which limits the AGC'ed output from the amplifier so that the signal reaching the slow response wideband filter means never exceeds a predetermined value which would cause distortion in the feedback loop. The output of the novel automatic gain control circuit is coupled to a despreading circuit which removes substantially all of the remaining burst jamming signals.

Abstract: A phase detector for a multi-channel PSK receiver is provided with a plurality of phase channels. Each of the phase channels has its own comparator coupled to an electronic switch for producing signals which are the products of the analog data inputs on the phase channels. The outputs from the electronic switches are connected to positive and negative summing circuits and the output of the positive and negative summing circuits are connected to the positive and negative inputs of a differential amplifier which produce a sum of the difference of the absolute value of the analog data inputs which is employed as an error voltage signal to control the frequency of a voltage controlled oscillator in a multi-channel PSK receiver. By eliminating convention analog multipliers in the phase detector, the phase detector is capable of generating error voltage signals from analog data input signals having data rates as high as 5 gigabytes per second.

Abstract: A single stage power conditioner which produces an isolated DC output while drawing resistive input current from the utility has been described. A high frequency switch-mode technique was used which operates in continuous conduction mode to reduce electro-magnetic interference (EMI) generation and ripple losses.

Abstract: A liquid cooled integrated circuit module includes a substrate, a plurality of chips mounted on the substrate, and electrical conductors integrated into the substrate to interconnect the chips. A compliant member which is completely seamless overlies all of the chips. This seamless compliant member is hermetically sealed at its perimeter to the substrate around all of the chips. Between this seamless compliant member and the chips are thermally conductive studs, and they carry heat by conduction from the chips to the compliant member. A rigid cover overlies the compliant member, and it is attached to the substrate at its perimeter. Within the cover are several parallel spaced apart ribs which project towards and press against the compliant member between the chips, and they form channels for a liquid coolant which carries heat away from the compliant member.

Abstract: The article of the invention is an optically readable label for storing encoded information, said label comprising a data energy of a multiplicity of information-encoded hexagons contiguously arranged in a honeycomb pattern, and having at least two different optical properties.A process for encoding information in an optically-readable data array comprised of a honeycomb of contiguous hexagons encoded by assigning optical properties to individual hexagons in a predetermined pattern, ordering the hexagons in a predetermined sequence, and printing the hexagons with at least two optical properties.A process for retrieving information by optically scanning an information-encoded data array of contiguous polygons, preferably hexagons, creating an optical replica of the digital bit stream representative of the optical properties of the information encoded polygons, decoding that optical replica and retrieving the decoded bit stream.A stream for performing the foregoing encoding and decoding processes.

Abstract: A vector file organization for a multiple pipelined vector processor with data transfer capability to support multiple program execution pipelines. Multiple pipelines can simultaneously access various blocks of the vector file through segmenting the file storage and by addressing the various elements of the segments. Vector files of programmable registers each have storage for sixty-four elements of 36-bit words or thirty-two elements of 64-bit words. Six independent execution pipelines in combination can programmably access the vector files for either read operands or write operands or both. Each vector file has N independent blocks, each using a RAM with read output to the pipelines, an address register and a write data register. Each block holds interspersed word pairs of words of each vector file. Primary and secondary vector files are equal in capability and allow reading pairs of elements, as required by arithmetic instructions.

Abstract: A left justification scale factor generator is described which is capable of scaling numbers for binary number groups off one, two, three and four bit groups. Two basic building block circuits are utilized in the scale factor generator's priority encoder, which looks at four binary bits and produces a two bit binary count that corresponds to the first non-zero input found, and an algebraic priority encoder which also receives a reference signal that allows it to indicate the significance of the priority detection level. By sensing correction factors at the first level of the system, the number of logic levels are kept to a minimum.

Abstract: An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry.

Abstract: The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator.

Abstract: A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop and a tracking loop. The data detection loop is initially not coupled to the input of the voltage controlled oscillator in the tracking loop of the PLL, but is separated by an electronic switch. A phase lock detection circuit is provided which is coupled to the data detection loop and to the tracking loop for detecting the difference in the voltage error signals in the data detection loop and the tracking loop. When this error signal indicates that the tracking loop is locked on to the carrier signal the electronic switch is closed completing the phase locked loop circuit after lock on of the carrier is achieved.