Abstract: A multiple port memory includes a set of memory units each comprising a set of memory cells, one corresponding to each port. Each cell of a memory unit stores a single data bit and each cell is independently read and write accessed through separate data, address and control busses. The cells of each memory unit are cross-coupled so that when the state of the bit stored by one of the cells of a memory unit is changed when write accessed, the other cells of the memory unit thereafter change the states of their stored bits in the same way.

Abstract: A clock signal is transmitted to nodes of each of several interconnected circuits through a separate adjustable delay circuit, the time delay of each delay circuit being adjusted so that the clock signal arrives at each node at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor. The delay element monitor measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.

Abstract: A graphics display system (10) includes a display screen (14) on which images are formed and a data transform circuit (12) that provides transformations between model data representing the basic shape of an object and display data that are employed in the formation of an image of the object on the display screen. The model data are transformed into display data in accordance with position data and orientation data that correspond, respectively, to a translation and a rotation of the image on the display screen. The data transform circuit communicates with a central processing unit (30) that controls the operation of the graphics display system. The data transform circuit includes data storage registers (34, 36, 38, 40, 42, 44, 46) that receive and hold the model, position, and orientation data. A multiplier circuit (68) and an adder circuit (112) calculate the transformation of the model data into display data.

Abstract: Stored waveform records representative of respective repetitions of a repetitive signal are processed by reading a first waveform record from memory to form a reference signal. A second waveform record is read from memory to form a second signal, and the second signal is shifted in time in such a manner as to minimize the power of a difference signal, of which the instantaneous magnitude is representative of the difference in instantaneous magnitude between the reference signal and the time-shifted second signal. If the waveform records are identical but for jitter, and the power of the difference signal is brought to zero, this implies that the first waveform signal is synchronous with the processed second waveform signal, i.e., there is no jitter between the two signals.

Abstract: An interface circuit in a modular electronic system includes duplex control-signal transmission lines. Modules connectable to a controller unit of the system transmit configuration data items by way of the duplex lines to the controller during a first time period, and the controller during a second time period generates module control signals in accordance with the configuration of the modules. The module control signals are transmitted to the modules on the duplex transmission lines.

Abstract: A knock-out in the wall of the housing for electronic equipment is selectively removed to provide a knock-out opening. A wall includes first and second slits positioned along the boundary of the knock-out and separated by a land. The wall includes a break out opening adjacent to each land. Break portions of the wall separate the break out opening from the first and second slits. These break portions are severed to interconnect the first and second slits through the break out opening and permit removal of the knock-out. Plural such slits and break out openings are provided and arranged to provide a knock out of rectangular or other desired geometric shape. The slits and break out openings are sized to provide electromagnetic interference shielding. Also, the break portions are of a length which is approximately no greater than the thickness of the wall and are positioned to facilitate removal of the knock-out without deforming the wall and without leaving burrs in the knock-out opening.

Abstract: A record in which a color is represented on a record medium at a selected gray scale level is created by resolving an addressable area of the record medium into a square array of addressable record locations and organizing the record locations into a plurality of groups each containing a 4.times.4 array of record locations. The groups are organized into a plurality of dither cells each containing a 4.times.4 array of groups, whereby each dither cell contains 256 addressable record locations. An [i+(j.times.16)]th gray scale level is established within a selected area of the record medium, where i is an integer in the range from zero to 16, j is an integer in the range from zero to 16 and [i+(j.times.

Abstract: A circuit produces an output binary floating point number approximating with high accuracy the inverse of an input binary floating point number D in accordance with the expression (1/D).apprxeq.[(1/A)-C]+[C-(B/A.sup.2)], where the number A is a low accuracy approximation of D, and B is substantially equal to D-A. C is a number selected for each value of A such that the exponents of quantities [(1/A)-C] and [C-(B/A.sup.2)] are equal to the exponent of the quantity 1/2A. Quantities [(1/A)-C] and [C-(B/A.sup.2)] are produced by lookup tables and summed to provide an approximation of 1/D.

Abstract: In a computerized simulation system, the behavior of a model comprising a group of interrelated objects in an object oriented programming environment is defined by a constraint network including temporal constraints, which the future behavior of the model must satisfy following triggering events. Following a triggering event, time stamped representations of messages are created and stored in a queue. The value of a time variable representing time is progressively incremented and the message indicated by each enqueued representation is sent to the model as the value of the time variable surpasses the value of the time stamp of the representation. The message representations and the value of their time stamps are created according to the requirements of the constraint network such that the messages cause the model to perform the appropriate actions at the appropriate times in order to satisfy the temporal constraints defined by the constraint network.

Abstract: A rule acquisition method for expert systems receives input from the expert, one word at a time, and checks each word by determining alternative parses for the partial sentence as so far entered. Feedback is provided to the expert when a word does not conform to a required grammar, this feedback comprising a menu of legal next choices. When the sentence is completed it is translated into the form of a diagnositc rule. An expert system for troubleshooting electronic equipment is disclosed employing rules generated in the aforementioned manner.

Abstract: A signal viewing instrumentation control system includes a programmable test instrument, a computer having an input keyboard and/or mouse, a CRT display and a communications interface for the computer to communicate with the test instrument. The test instrument can be a digitizer, a spectrum analyzer, a power supply or a signal generator. The system includes software for the user to interactively control the test instrument through the computer. The software includes a functional characterization of the test instrument for inversely transforming a generic output for the instrument into a generalized set of control setting commands for controlling operation of the instrument. The user can graphically enter into the computer a user-specified output for the instrument. The computer converts the graphically-specified output into a specific set of the control setting commands and transmits the specific commands to the test instrument to control its operation.

Abstract: A time base circuit for a waveform sampling system produces a strobe signal for initiating waveform sampling an adjustable strobe delay time following detection of a triggering event in a waveform. The time base circuit includes a strobe control circuit for producing the strobe signal and a strobe sense signal in response to a strobe drive signal, a strobe drive circuit for generating the strove drive signal, an adjustable time after a trigger signal, and a trigger generator for producing the trigger signal in selective response to either the triggering event in the waveform or the strobe sense signal. The strobe signal delay time is calibrated by setting the trigger generator to produce the trigger signal in response to the strobe sense signal thereby causing the strobe drive circuit to generate the strobe drive signal periodically.

Abstract: An improved method and apparatus is disclosed for determining the internal state of a processor without disturbing the operational environment of the processor. A two phase process is employed. In the first phase, external signals produced by the processor in the execution of a known program are monitored and recorded for subsequent analysis. In the second phase, the recorded information is analyzed in the light of the known characteristic of the processor, the program it was executing, and the signals recorded during the first phase. The internal state of the processor is thereby determined after the execution of each instruction. In addition, provisions are made for the specification of breakpoints, and the examination of simulated status of the processor on the occurrence of the breakpoints.

Abstract: A high density connector in which the conductive leads of at least two circuit boards, two flexible circuits, or one of each are interconnected directly without the use of a traditional molded connector with pins captured therein. This is accomplished by overlapping the two boards with the conductive paths on each to be interconnected facing each other. An anisotropic elastomeric polymer material is inserted between the boards and then the sandwich is clamped together compressing the polymer material to provide a low electrical resistance path therethrough to interconnect the conductive paths on the respective circuit boards. One disclosed embodiment utilizes backing plates above and below the sandwich with a plurality of screws passing through registration holes to align the conductive paths and to provide closure of the connector. The other disclosed embodiment is designed to interconnect two boards along substantially the full width of the boards.

Abstract: An apparatus for generating a trigger signal in response to a selected pattern of events includes event synchronizers for generating synchronized event signals of states indicating the current state of each event on the falling edge of each pulse of a clock signal. A programmable encoder provides a set of event encoding signals of states set according to selected patterns of synchronized event signal states. A set of bus drivers actively drives the potential of each conductor of a bus high on the falling edge of each clock signal pulse and actively drives the potential of selected conductors of the bus low on the rising edge of each clock signal pulse, the conductors being selected according to the pattern of event indicating signal states generated by the encoder.

Abstract: A two-dimensional array of binary values is used to control operation of a bi-level imaging device. The array of binary values is formed by applying an enhanced array g(u,v) to a two-dimensional array of threshold values. A two-dimensional array of pixel value f(u,v) is used to form the enhanced array g(u,v) such that g(u,v)=m.sub.f +k[f(u,v)-m.sub.f ] where m.sub.f is the average value of f(u+a, v+b) from a=-L to a=+L and b=-M to b=+M and k is a gain function which depends on the standard deviation in f(u+c, v+d) from c=-N to c=+N and d=-P to d=+P. L, M, N and P define the sub-array over which the standard deviation is calculated. Preferably, L, M, N and P are each equal to 2. The value of k is a decreasing function of the standard deviation: the larger the standard deviation, the smaller the gain factor k. The rate at which k decreases with increase in the standard deviation depends on the edge sampling characteristics of the array of threshold values.

Abstract: A delay circuit generates an output signal that changes state in adjustably delayed response to a state change in an input signal, the delay being adjusted by a control signal. A series of buffers produces a plurality of delayed signals that change state at different times in response to state changes in the input signal. Amplifiers amplify the input and each delayed signal to produce output currents that are summed to provide a load current through load resistors, thereby providing the output voltage across the load resistors. The gain of each amplifier is adjusted in accordance with the control signal such that at least one and not more than two of the amplifiers have non-zero gain. The delay provided by the delay circuit is determined by the relative gains of the amplifiers.

Abstract: A delay element for producing an output signal in response to a change in state of an input signal includes variable gain first and second amplifiers and a delay buffer having a fixed delay. The input signal is applied as input to the first amplifier and the delay buffer while the output of the delay buffer is applied as input to the second amplifier. The outputs of the first and second amplifiers are summed to provide the output signal. When the gain of the first amplifier is high and the gain of the second amplifier is low, the output signal will respond to the change in state of the input signal with minimum delay. When the gain of the first amplifier is low and the gain of the second amplifier is high, the output signal will respond to the change in state of the input signal with maximum delay.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.