Abstract: A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive.

Abstract: Various types of articles having various deposition coatings applied using a gas vapor deposition process are provided. A system evacuates gases from the article or a deposition chamber prior to depositing a coating. The coating may be applied throughout the inside of an article or may be selectively applied to a portion of the article. The article may be moved relative to the gas jet or the gas may be moved jet relative to the article. Stencils may be used to pattern the coating on the surface of the article. The articles are coated in a pressure of approximately 5 millitorr. Articles may be cylindrically shaped, leadframes on a reel, substrates, or printed circuit boards.