Abstract: An MOS random access memory cell using the capacitance of a buried P-N junction as the storage element is formed by a process compatable with standard N-channel silicon gate manufacturing methods. The cell is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, a buried, fully implanted charge storage element which also is the source of the cell transistor, self-aligned polysilicon gates, multilayer oxide and a thin film of metallization for interconnections. The vertical stacking of the charge storage and transfer elements and the increase in storage area to cell area ratio with the buried storage area provide a cell with very high packing density.

Abstract: An improved MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a self-aligned gate process which consists of an implanted channel stopper underneath a thick field oxide, depletion and enhancement mode device channel implants, implanted source and drain regions, selective oxidation to form self-aligned gates, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Abstract: A MESFET integrated circuit device with a metal-semiconductor diode as the control element and a source and drain as other device elements is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, implanted source and drain regions, depletion and enhancement mode device channel implants, metal-semiconductor junctions as control elements, barrier metal and a thin film metallization system. The process and device structure are suited for high packing density, very low speed power product and ease of fabrication making it attractive for digital applications.

Abstract: The invention is embodied in a novel method of forming titanium dioxide layers for metal-insulator-semiconductor device dielectrics. The titanium dioxide of a type known as rutile is formed by the deposition of titanium metal upon a layer of silicon dioxide and oxidation of titanium in an oxygen ambient at high temperatures.