Abstract: A method and apparatus provide a video image of facial features synchronized with synthetic speech. Text input is transformed into a string of phonemes and timing data, which are transmitted to an image generation unit. At the same time, a string of synthetic speech samples is transmitted to an audio server. The audio server produces signals for an audio speaker, causing the audio signals to be continuously audibilized; additionally, the audio server initializes a timer. The image generation unit reads the timing data from the timer and, by consulting the phoneme and timing data, determines the position of the phoneme currently being audibilized. The image generation unit then calculates the facial configuration corresponding to the position in the string of phonemes, calculates the facial configuration, and causes the facial configuration to be displayed on a video device.

Abstract: The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.

Abstract: A Faraday shield minimizes the leakage of electromagnetic interference (EMI) and radio frequency interference (RFI) of a maximum frequency and corresponding wavelength that emanates from electronic components contained within the shield. The top and bottom each contain apertures that are dimensioned to effectively block the escape of EMI and RFI from the shield and to permit the flow of air to dissipate heat without generating acoustic noise. The thickness of the top of the shield is at least one half of the diagonal length across the largest of the apertures located in the top. The length of the longest aperture side is less than one fourth of the wavelength of the maximum frequency of EMI and RFI contained by the shield. Corresponding relationships exist between the apertures located in the shield bottom and its thickness.

Abstract: Computer systems using a processor that is capable of operating in a system management mode (SMM) employ a dedicated system management RAM (SMRAM). The processor uses the SMRAM when the processor is performing a task associated with the SMM. The processor is capable of generating a range of system addresses. The range includes a particular subrange of system addresses that are used for accessing the SMRAM. A memory controller decodes the system addresses generated by the processor and enables access to the SMRAM, regardless of whether the processor is operating in the SMM, when the controller decodes a system address of the particular subrange. The range of system addresses also includes a second subrange. The memory controller also enables access to the SMRAM when the processor is operating in the SMM and the controller decodes a system address of the second subrange. The memory controller indicates to the processor whether data associated with the enabled SMRAM can be stored in a cache memory.

Abstract: A method, and apparatus for its use, for reducing the number of disk accesses needed to satisfy requests for reading data from and writing data to a hard disk. A non-volatile cache memory used to hold data blocks for which write requests have been made is purged of "dirty" blocks, not yet written to the disk, based on the proportion of dirty blocks in relation to an upper threshold and a lower threshold. A purge request flag is set when the proportion of dirty blocks goes above the upper threshold, but is not cleared until the proportion of dirty blocks goes below the lower threshold. So long as the purge request flag is set, dirty blocks are purged when the disk is not busy with read requests. Immediate purging is initiated when the write cache becomes totally full of dirty blocks.

Abstract: A communications network has a plurality of users connected by virtual circuits to a plurality of service providers. A server has the plurality of users connected thereto. A node provides the plurality of service providers. Both the server and the node are connected to the network. A first session is established between one user and the server, and a second session is established between the node and a selected one of the service providers. A virtual circuit is established linking the first service session and the second service session to establish message transmission between the one user and the selected service provider. A message sent between the user and the service provider is sent over the network, and the message identifies the virtual circuit. Messages between a server and a node are multiplexed by having slots, and a slot contains a message from a sending session to a receiving session.

Abstract: A memory controller circuit for use in a computer system provides memory address and control signals to a single in-line memory module (SIMM) connector. The SIMM connector can hold a SIMM that has dynamic random access memories (DRAMs) mounted on one or both sides. The SIMM connector provides a channel of signals to both sides of the SIMM. A driver associated with each channel receives a memory address and control signal. Each driver either drives a buffered memory signal to the associated channel or is placed in a high impedance state, depending upon whether a SIMM is in the SIMM connector. If a SIMM is in the connector, the driver associated with one of the channels is placed in the high impedance state if it is determined that the SIMM is single-sided. A programmable disabling means provides a driver enable signal to each driver. When the driver enable signal is asserted, the corresponding driver is in an enabled state. A deasserted driver enable signal places the corresponding driver in a disabled state.

Abstract: A memory monitoring system equips a computer program for monitoring its own memory accesses. The system employs special values, called "VALUEA" and "VALUEB," stored in the memory locations and a table of write tags, each preferably a single-bit flag corresponding to a different one of the memory's locations. If the write tag is not set for a particular memory location, VALUEA within that location indicates that it is unallocated, and VALUEB indicates that it is allocated and not initialized. The write tags can be set to indicate that the corresponding memory location contains written data. The program so equipped can monitor each memory access, including, e.g., allocation, write, read, and memory freeing operations, using the combination of the location contents and the write tag table to determine valid memory operations and to signal memory access violations. Counters can be provided to track the number of valid accesses of particular types and/or of valid accesses to particular locations.

Abstract: A SCSI adapter for interconnecting first and second SCSI buses includes a filter for preventing BUSY glitches from being passed from one bus to the other. The filter includes a shift register connected to NAND logic. The SCSI adapter also has a circuit for establishing a desired timing relationship between DATA signals received over the first bus and corresponding ACK or REQ signals also received over that bus that indicate whether the DATA signals are valid. The circuit includes a DATA latch responsive to a delayed version of the ACK or REQ signal received at a clock input thereof. The output of the latch and the corresponding delayed ACK or REQ are transmitted over the second bus.

Abstract: The invention improves the efficiency of buffer descriptor processing by performing descriptor prefetches, where multiple descriptors are read within the same descriptor bus transaction. The invention reads multiple buffer descriptors each time the bus is accessed. This allows for a smaller FIFO in a cut-through network adapter because it reduces the number of bus transactions needed to transfer data.

Abstract: A memory resource allocation look ahead system is implemented in event logger (14), operating in conjunction with one or more event sinks (18). When the event logger (14) is called, all information in the argument fist is copied into an event buffer maintained by the logger (14), and the buffer is placed at the input end of queue (44). The event sinks 18 contain a similar queue. In operation of the event logger 14, an evd.sub.-- get.sub.-- event routine is used to obtain event reports from the event queue (44). The evd.sub.-- get.sub.-- event routine includes a next.sub.-- size.sub.-- hint argument, giving the size of the event record that will be obtained with the next call to evd.sub.-- get.sub.-- event. The next.sub.-- size.sub.-- hint argument is used to allocate memory for the next call to evd.sub.-- get.sub.-- event.

Abstract: A very thin portable computer includes a computer housing for holding electronic components and a battery housing movably mounted external to the computer housing, the battery housing adapted for holding batteries for supplying power to the electronic components. The battery housing is rotatably mounted on the computer housing such that the battery housing rotates between a closed position wherein the battery housing covers the rear side of the computer and an open position wherein the battery housing exposes connectors on the computer housing and elevates the rear side of the computer housing to an angle convenient for typing.

Abstract: A packet forwarding node for a computer network comprises at least one receiving module and at least one output module including packet list (21) for maintaining a list of packets to be transmitted therefrom. The time for which a packet remains in the node is determined by grouping the packets into groups or "buckets" which are created at regular intervals, each bucket containing packets arriving within the same time interval, and keeping track of the age of each bucket. A bucket counter (33) counts the total number of buckets in existence, so indicating the age of the oldest packet. This counter is incremented by 1 at regular intervals and decremented by 1 each time the oldest bucket is emptied (or found to be empty). A bucket list shift register (30) has its contents shifted at each change of time interval, and its the bottom stage accumulates the number of packets arriving in a time interval, and an overflow accumulator (31) accumulates counts shifted out of its top end.

Abstract: A read buffering system employs FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When the system sees a read command from the CPU, it stores an incremented value of the address of the read command in a history buffer and marks the entry as valid. The system detects a stream when a subsequent read command specifies an address that matches the address value stored in the history buffer. Upon detecting a stream, the system fetches data from DRAMs at addresses that follow the address of the subsequent read command, and stores it in a FIFO. However, to reduce unnecessary prefetching, the system looks for a read X, write X, read X+1 (where X and X+1 designate addresses) succession of commands so as to prevent them from creating a stream. This succession occurs often and qualifies as a stream, but is seldom followed by other reads that maintain the stream.

Abstract: A storage system having a plurality of disks arranged into a RAID array and a logging process and apparatus that identifies corrupt or invalid data and which prevents the corrupt or invalid data from being sent to a user application or used in any computations internal to the functioning of the array. In the preferred embodiment, a plurality of status bits, each having a first and second state are associated with each data block and parity block. If the status bit indicates that the block may contain corrupt or invalid information then that block is not used in regenerating data for an unavailable block or sent to a user application upon a read request.

Abstract: Method and apparatus for automatically closing gaps prior to painting a cel in a vector-based computer-aided drawing system. A drawing is processed, as it is entered by a user, to generate a stored planar map containing geometric and topological characteristics of the drawing. The planar map is searched to identify gaps and updated to store synthesized gap-closing vectors for those gaps smaller than a selectable size. The gaps are closed before the painting of the cel, or coloring of the drawing, so as to prevent unintended spill-over of the color into adjacent regions.

Abstract: In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Abstract: A heat dissipating arrangement in a portable computer uses a copper slug disposed between a heat-generating central processing unit (CPU) chip and the underside of a metallic keyboard baseplate. The slug also extends through a copper-plated hole in a printed circuit (PC) board, and is either soldered to the copper plating or press-fit into the hole to enhance heat transfer between the slug and the PC board. Small through-holes extend through the PC board and the copper plating next to the opening. These through-holes connect the copper plating to several layers of etch within the PC board, so that these layers act like fins on a heat sink to increase heat transfer away from the CPU.

Abstract: A correlation system communicates with preprocessors and a debugger in a translation system to correlate symbols and code segments of an input user program with symbols and code segments of an output executable version of the program. The correlation system stores information relating to changes to symbols and code segments made by each preprocessor in input correlation tables associated with input files and output correlation tables associated with output files of each preprocessor. The information includes pointers that depict the translations of the symbols and code segments, and information which characterizes the translations as exact, inexact or name change correlations. When the user identifies a symbol or a code segment in an output file, the debugger extracts the symbol name and code segment information from the output correlation table to identify the corresponding symbol or code segment in the input file.

Abstract: An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an SMRAM status bit corresponding to each data entry. The SMRAM status bit is set if the data entry holds data in SMRAM, and reset if the data entry does not hold data in SMRAM. The SMRAM status bit distinguishes SMRAM data from system memory data in the cache, thereby eliminating cache coherency problems.