Abstract: A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.
Type:
Grant
Filed:
November 2, 1988
Date of Patent:
November 10, 1992
Assignee:
International Business Machines Corporation
Inventors:
William C. Brantley, Jr., Harold S. Stone