Abstract: A radial power combining scheme is provided for combining a plurality of field-effect transistor-based amplifiers to form an amplifier circuit. The amplifier circuit includes input terminals for receiving high frequency power signals. A radial line power combiner/divider is provided for dividing the input signal amongst a plurality of amplifiers. The radial line power combiner/divider is further adapted to receive and combine the amplified signals which are then provided to an output. The circuit advantageously utilizes a plurality of three-port circulators for transmitting the signals within the circuit.

Abstract: An improved memory module structure for use in a large memory in which, before operational use, the memory modules are tested and configured by a process that requires storing logical page addresses into a page register in each module. In this module, page address data are input to the page register from a data input line to the module. Since there is a separate data input line for each module in a column of such modules, and since the data input lines are not used to carry data to the memory in a test and configuration mode, the data input lines can be used to supply page address data simultaneously to the page registers of an entire column of modules. This avoids having to address each module in the column individually, and reduces testing an configuration time by a factor equal to the number of modules in a column. The complexity of each module is also reduced by obviating the need for individual module addressing in the test mode.

Abstract: A 51/2" by 53/4" flat ceramic board is bonded to an aluminum frame which serves as a heat sink. The bonding agent intermediate the board and the frame is thermally conductive and comprises an epoxy containing Master Bond EP21TDCAOHT. The formed laminate or bond is capable of withstanding repeated stresses occurring through thermal cycling in temperatures from -60 degrees centigrade to +125 degrees centigrade and vibration and humidity testing.

Abstract: A surface acoustic wave (SAW) chirp signal processor having a piezoelectric substrate, an array of input transducers and an array of output transducers. In its chirp compression mode, the device has chirp signals applied in parallel to its input transducers and produces compressed output pulses at its output transducers, corresponding to selected chirp rates. The input transducers are successively offset with respect to a focal point on the array of output transducers, by distances that successively and linearly increase or decrease from transducer to transducer, consistent with the increase or decrease in the wavelength of the chirp signals. The device may also be used in a pulse expansion mode, by inputting a broadband pulse into a selected one of the output transducers. The input transducers then produce a chirp signal having a rate corresponding the selected to output transducer.

Abstract: An adaptaive nulling antenna control system (24) which is effective in constraining pulse jammer duty factors. The system (24) accepts signals from a multibeam antenna (40) in a coded communication network (10). A band stop filter (50) removes the communication signal and analyzes the various antenna channels to form a nulling signal which is then combined with the original antenna signal to effectively null the jamming signal in those directional channels in which the jamming signal appears. The system (24) utilizes a successive over-relaxation type algorithm featuring scaling, eigenvalue shifting, and adaptive memory to give a fast attack time and slow release. The system (24) can be implemented in a pipeline architecture to further increase processing speed.

Abstract: This invention discloses a processing structure, and related method, for performing a selected data processing function by means of multiple processing modules that are selected to perform the selected function when appropriately connected together. The modules are removably connected to a common structure, such as a circuit board, which has associated with it a crossbar switch for providing intermodule data connections necessary for performing the selected function, and a synchronization unit for providing control signals to the modules to keep them in appropriate synchronism for performing the selected function. Convenient reconfiguration of the structure is effected by conditioning the crossbar switch and the synchronization unit as necessary to perform the different function.

Abstract: A probabilistic or stochastic artificial neuron in which the inputs and synaptic weights are represented as probabilistic or stochastic functions of time, thus providing efficient implementations of the synapses. Stochastic processing removes both the time criticality and the discrete symbol nature of traditional digital processing, while retaining the basic digital processing technology. This provides large gains in relaxed timing design constraints and fault tolerance, while the simplicity of stochastic arithmetic allows for the fabrication of very high densities of neurons. The synaptic weights are individually controlled by a backward error propagation which provides the capability to train multiple layers of neurons in a neural network.

Abstract: A generally planar antenna structure having at least six radial antenna elements, each of which uses log-periodic principles to provide a broad bandwidth of operation. Each antenna element has a radial arm and integral, arcuate teeth extending in opposite directions from the radial arm, such that the spacing, width and length of the teeth increases with increasing radial distance from the center of the structure. The teeth are preferably interleaved with teeth in adjacent antenna elements. A feed region of the structure is provided near its center, to connect the antenna elements through a connection matrix to input/output terminals and provide operation in multiple modes and multiple polarization senses.

Abstract: A combination of doubly folded parallel plate beam combiners or dividers, configured to produce a desired composite beam for use in arrays of antenna elements. The doubly folded combiner or divider functions to expand a transmitted beam, or contract a received beam, in one selected plane. In a transmit mode, a single beam can be expanded first in one direction by a first divider, then expanded in a perpendicular direction by a stack of additional dividers coupled to the first. Optional phase shifting circuits provide beam steering as desired. Second and other additional beams can be processed in the same manner, to produce a composite output of multiple beams for transmission by an antenna array. Another aspect of the invention involves the use of a beam forming structure of this type in conjunction with an array of transmit/receive microwave modules providing amplification and phase shifting functions, and an array of printed circuit antenna elements.

Abstract: A technique for producing high reliability GaAsAlGaAs heterojunction bipolar transistors by Molecular Beam Epitaxy with beryllium base doping. Beryllium incorporation and diffusion, during base-layer deposition, is controlled through a combination of reduced substrate temperature and increase As/Ga flux ratio during MBE growth resulting in extremely stable heterojunction bipolar transistor profiles. In addition, graded InGaAs surface layers with non-alloyed refractory metal contacts are shown to significantly improve ohmic reliability to alloyed AuGe contacts. High gain (DC beta) is achieved by the use of an increased substrate temperature during emitter deposition. The HBTs in accordance with the present invention are useful in a number of important microwave applications such as log amps, a/d converters, and sample and hold circuits where high reliability is desired.

Abstract: A technique for reducing the undesirable effects of amplifier offset voltages in quantizers such as analog-to-digital converters and related devices. The quantizer of the invention has an array of input amplifiers for comparing an input signal with multiple reference voltages, an array of latches for registering output signals from the amplifiers, and signal summing circuitry connected between the amplifiers and the latches, to produce a set of modified amplifier outputs for input to the latches, each of the modified amplifier outputs being derived from a weighted sum of at least three amplifier outputs. In the event of a defect in one or more amplifiers causing unwanted amplifier offsets, the summing circuitry improves linearity without the need for paralleling of transistor components. In one embodiment of the invention, the summing circuitry includes a resistor ladder to which the amplifier outputs are connected and from which the modified outputs are derived.

Abstract: This invention discloses an infrared detector which separates current induced by incident gamma ray radiation for use in a radiation environment. The infrared detector includes a semiconductor which includes a first layer heavily doped with n-type atoms, a second undoped layer and a third layer lightly doped with n-type atoms. At least one heavily doped n-type contact region and one heavily doped p-type contact region are embedded in the third layer. Both incident gamma ray photons and infrared photons release charge carriers in the second layer which travel as conduction current through the semiconductor. Since gamma rays are of high energy, they can release electrons from the valence band into the conduction band. When an electron is released from the valence band a hole is generated in its place which acts as current charge carrier. The electron released into the conduction band travels to the first layer and the hole travels to the p-type contact region under the influence of an electric field.

Abstract: A choke-slot ground plane and antenna system 30 is disclosed. In one embodiment the choke-slot ground plane and antenna system 30 includes a monopole antenna 44, a ground plate 36 having a plurality of concentric annular grooves 38a-c. Other embodiments include a ground plane 36 having varying size grooves to 38a-l, a ground plane having grooves having filled with dielectric material 38a'-c', a ground plate having a broadened bandwidth and having a series of first and second-type grooves 34a-c and 38a"-c", and a ground plate having a frusto-conical shape 36a and 36b.

Abstract: A W-band waveguide variable controlled oscillator incorporating a capacitively coupled Gunn diode and varactor diode arranged in such a manner that adverse environmental conditions do not deleteriously effect the stability of the output of the oscillator. The Gunn diode is electrically connected to a waveguide chamber within the oscillator and includes a resonator electrically connected to its end cap. The resonator is electrically connected to a DC bias source by means of a DC bias filter and a wire inductor. Opposite and above the Gunn diode is a varactor assembly including a varactor diode, which is also electrically connected to a DC bias source through a DC bias filter. A variable coupling spacer within the varactor assembly adjusts the distance between the varactor diode and the Gunn diode such that the capacitive coupling between the two can be adjusted. In addition, an adjustable back-short is incorporated within the waveguide channel to adjust the power output of the oscillator.

Abstract: An improved miniature interconnect (10) for detachably introducing a transmission line (12) to a corresponding medium (20) through a passage in a barrier (18). This interconnect (10) comprises a fastening means (36), coupled to the transmission line (12) for directly engaging the passage such that the transmission line (12) is removably retained in a held relationship with respect to the barrier (18). A conducting means (38) for establishing electrical contact between the transmission line (12) and the corresponding medium (20) is disposed within the passage and is engaged by both the transmission line (12) and the corresponding medium (20). This conducting means (38) further provides a sealing means (42) for sealing the passage through the barrier (18).

Abstract: A lightweight, compliant, high strength fabric providing controlled stretch, and a process for its manufacture. The fabric is consolidated into a unitary structure from a single stacked-film matrix of one or more thin elastomeric films, each having at least one reinforcing fiber embedded in the film in a sandwich construction. The reinforcing fibers are buckled along their length when the film is in a relaxed state, and if more than one fiber, arranged in a generally parallel relationship with each other within each elastomeric film. The stacked elastomeric films are cross-plied such that the courses of fibers in the separate films are aligned in selected multiple directions, with each course of fibers lying in its own plane. Stretching of the fabric in any of the selected multiple directions is uninhibited by the buckled fibers but is limited when the fibers reach a straightened condition. As the fabric stretches, the fibers straighten, eventually limiting the stretch of the fabric as the fibers become taut.

Abstract: A memory circuit for controlling writing and reading operations in a large semiconductor memory having multiple modules, some of which are subject to production or environmentally caused defects. Memory modules are arranged in columns and there is a column interface for each column, each module being connected to its column interface by a single-bit data line. Each column interface includes a configuration register that is used to record an association between the memory modules in the column and selected data bit positions of an external data word. The same association is used both during writing operations, wherein data words are written from the data bus to the memory modules, and during reading operations, wherein data words are read from the memory modules to the data bus.

Abstract: A digital-to-analog (D/A) converter using cyclical current source switching to average out the errors in individual current sources. The D/A converter includes a current source switching circuit, a bank of constant current sources and a control circuit. The current source switching circuit, which is clocked by the control circuit, generates an upper and a lower pointer in accordance with a digital input signal. The upper pointer, which is advanced for an increasing digital input signal, connects current sources to an output bus. The lower pointer, which is advanced for a decreasing digital input signal, disconnects current source from the output bus. The upper and lower pointers continuously cycle through the bank of current sources to average out the errors in the individual current sources.

Abstract: A family of logic circuits using nonhysteretic superconducting quantum interference devices (SQUIDs) connected together to perform various functions using a common operating principle. Each circuit has an output line, first and second power supply lines having first and second voltage states, and input lines that can have one of the two voltage states. A pull-up circuit, having at least one SQUID, is connected between the output line and the first power supply line, and the input lines are coupled to the pull-up circuit in such a manner as to pull the output line to the first voltage state only if the input lines conform with a selected combination of voltage states. A pull-down circuit, also having at least one SQUID, is connected between the output line and the second power supply line, to pull the output line to the second voltage state only when input lines do not conform with the selected combination of voltage states.

Abstract: A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.