Abstract: A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

Abstract: A method for display of near video on demand programs broadcast over a network system to a receiver operable to record at least one channel. The program includes a plurality of segments broadcast over two or more channels during a plurality of time intervals. The method includes displaying a first segment of the program as it is broadcast at a first time interval and recording a second segment of the program at the first time interval if the second segment is not scheduled for broadcast at a second time interval. The second segment is displayed if broadcast at the second time interval or the recorded second segment is played at the second time interval if not broadcast. The steps of recording and displaying are repeated for remaining segments of the program until the last segment of the program is displayed. A method for scheduling broadcast of near video on demand programs and a system for displaying near video on demand programs are also disclosed.

Abstract: A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment, if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation.

Abstract: A system and method for providing a graphical user interface (GUI) in an interactive television system. In the preferred embodiment, the interactive television system comprises a video delivery system for providing video content, and at least one subscriber television including a display screen, wherein the subscriber television is coupled to the video delivery system. According to the present invention, the video delivery system provides a compressed background picture and one or more compressed insert pictures. Each of the compressed insert pictures represents a display portion of the GUI. The subscriber television receives the compressed background picture and the one or more compressed insert pictures, and operates to paste at least one of the compressed insert pictures into the compressed background picture. The pasting is preferably performed in response to interactive program execution and/or user input.

Abstract: A computer implemented method and a computer program product includes a first computer readable code construct configured to handle request messages. This comprises receiving a request message and having an associated user name which is associated with a remote user on a network. Further, making an access determination to determine whether the forwarding of the request message is authorized, and finally when forwarding of the request message is authorized, the message to a target system is forwarded.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: A method and apparatus for detecting errors in a First-In-First-Out buffer (FIFO). A FIFO includes verification bits associated with data entries. In addition, the FIFO includes an expected value bit for comparison on reads. Upon reset, the verification bits are initialized to an alternating sequence of binary values and the expected value bit is initialized to a predetermined binary value. On a write to a FIFO entry, the corresponding verification bit is toggled. On a read from an entry, the corresponding verification bit is compared to the expected value. If the verification bit does not match the expected value, an error is detected.

Abstract: A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

Abstract: An interactive television system configured to display an animated character which has an appearance indicative of a viewer's interaction and time spent watching a particular television program. In one embodiment, the character is a genie which appears more healthy when the viewer's watching/interaction increases and less healthy when it decreases. Various features of the genie, such as hair color, clothing and name, are viewer-selectable. The genie may prompt the viewer for responses, which responses result in the awarding of points to the genie, which in turn make it appear more healthy or give it certain powers or characteristics. The genie is implemented in an interactive application which is transmitted to a set-top box coupled to the viewer's television. Transmission of related data through a return path to the broadcast station which originated the application enables the viewer to participate in lotteries and other special promotions.

Abstract: A branch prediction unit includes a local branch prediction and a global branch prediction. A global branch prediction utilizes a global history shift register to record the behavior of conditional branches. In some cases, a conditional branch may behave in a static manner, either always being taken or not taken, while resident in an instruction cache. Such static behaving conditional branches do not need a global history for prediction and contend with other conditional branches for global branch history training. By utilizing a dynamic branch classification scheme, branches requiring global history prediction can be identified and static behaving conditional branches may be prevented from polluting the global history. All conditional branches are initially classified as local and do not participate in global history training. Only after two mispredictions are branches recognized as exhibiting dynamic behavior and classified as global.

Abstract: A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which updates only a portion of a destination register and a subsequent instruction which requires a larger portion of that destination register, inclusive of the smaller updated portion, as a source. To resolve such dependencies between instructions, a determination is made upon decode of an instruction whether it updates only a portion of a destination or the entire destination. If only a portion of the destination is updated by the instruction, a read of the destination is done prior to execution of the instruction and the data read from the destination is merged with the results of the instruction execution. The merged data is then conveyed as the results of the instruction execution.

Abstract: A system and method for generating trick play video streams, such as fast forward and fast reverse video streams, from an MPEG compressed normal play bitstream. The system receives a compressed normal play bitstream and filters the bitstream by extracting and saving only portions of the bitstream. The system preferably extracts I-frames and sequence headers, including all weighting matrices, from the MPEG bitstream and stores this information in a new file. The system then assembles or collates the filtered data into the proper order to generate a single assembled bitstream. The system also ensures that the weighting matrixes properly correspond to the respective I-frames. This produces a bitstream comprised of a plurality of sequence headers and I-frames. This assembled bitstream is MPEG-2 decoded to produce a new video sequence which comprises only one out of every X pictures of the original, uncompressed normal play bitstream.

Abstract: A system and method implemented in an interactive television system for managing modules of interactive television applications. The system transmits modules from a broadcast station to a plurality of receiving stations through various paths, such as broadcast channels and modem channels. The receiving stations have module managers which store module requests and which monitor the various channels for modules corresponding to the requests. When modules are transmitted on the monitored channels, they are matched with the corresponding stored requests. If a module matches one of the requests, or if is an auto-loading module, it is stored in the receiving station. If a module has not been requested and is not an auto-loading module, it is ignored. The stored modules are added to a list of modules available for execution or for use by an executing application, and the corresponding requests are deleted.

Abstract: An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

Abstract: A system and method implemented in an interactive television system for scheduling delivery of modules of interactive television applications from a broadcast station to a receiving station. In one embodiment, the system calculates a start time from a predetermined end time and transmission interval for a module. In other embodiments, a transmission interval may be calculated instead of being predetermined, or all of the scheduling information may be explicitly provided to the broadcast station. The module is packetized and transmission of the packets for the module is begun at the corresponding start time. All of the packets except the last packet are transmitted within the transmission interval (i.e., between the start time and the delivery time.) The greater the transmission interval, the greater the flexibility the broadcast station has to schedule delivery of the packets and modules. The last packet is held until the scheduled delivery time and is then transmitted.