Abstract: A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.

Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.

Abstract: A method of fabricating trenches has been achieved. The method may be applied to damascene and dual damascene contacts to prevent damage to organic low dielectric constant materials due to photoresist ashing. A semiconductor substrate is provided. A first dielectric layer is deposited overlying the semiconductor substrate. A first etch stopping layer is deposited overlying the first dielectric layer. A second etch stopping layer is deposited overlying the first etch stopping layer. An optional anti-reflective coating is applied. A photoresist layer is deposited. The photoresist layer is patterned to define openings for planned trenches. The second etch stopping layer is etched through to form a hard mask for the planned trenches. The photoresist layer is stripped away by ashing where the first etch stopping layer protects the first dielectric layer from damage due to the presence of oxygen radicals.

Abstract: A new method of fabricating shallow trench isolations has been achieved. No final polishing down process is needed. A silicon substrate is provided. A pad oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the pad oxide layer. The silicon nitride layer, the pad oxide layer, and the silicon substrate are patterned to form trenches for planned shallow trench isolations. A liner oxide layer is grown overlying the semiconductor substrate is the trenches. A silicon dioxide spacer layer is deposited overlying the silicon nitride layer and the liner oxide layer to partially fill the trenches. The silicon dioxide spacer layer and the liner oxide layer are anisotropically etched to form sidewall spacers inside the trenches and to expose the bottom of said trenches. A silicon layer is selectively grown overlying the semiconductor substrate in the trenches. The silicon layer partially fills the trenches. A trench oxide layer is formed overlying the silicon layer.