Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: A programmable logic gate array employing a plurality of reprogrammable fuses having a logical NAND characteristic for logically connecting selected inputs to selected logic gates. The fuses are selectively programmed for providing appropriate signals to allow three modes of operation of the logic gate array; programming, erasure and normal logic operation.

Abstract: An impedance transforming circuit for multibit digital word signals includes plural transmission paths for respective signals of a word. At least some of the paths have different output impedances but present essentially the same signal propagation delay. Each path includes plural, tandem connected, transistor switches; and each switch comprises, with correspondingly located switches of other paths, a stage of the transforming circuit. Output conductances of the switches of a path are scaled along the path according to a stage-to-stage ration F selected to minimize the number of stages required to achieve a desired signal propagation time through the path. At any stage switch where the ratio F cannot be directly accommodated, the selected value of F is achieved by dividing the stage output conductance between an in-path switch, that satisfies that ratio F with respect to a driven stage and a dummy-load switch that, together with the in-path switch, satisfies the ratio F with respect to a prior stage switch.

Abstract: A monolithic integrated circuit (IC) chip in which is formed a multi-driver power circuit, with each driver circuit including one output power transistor, is partitioned such that the power transistor of each driver circuit, formed in the IC, is spaced apart from those of any other driver circuit a distance sufficiently large to ensure the generation of a temperature differential between the power transistors of the different driver circuits when their power dissipation is different. A thermal sensor is formed in close proximity to each output power transistor, and as far away as possible from the other power transistors of the IC, whereby each thermal sensor is thermally, tightly, coupled to its associated power transistor. Each thermal sensor is electrically coupled to the base of its associated power transistor for controlling the conductivity of its associated power transistor when the power dissipation of its associated power transistor and its resulting temperature exceeds a predetermined level.

Abstract: A zener diode is connected at one end via a first impedance to a first power terminal. The base-to-emitter junctions of first and second transistors are connected in parallel between the other end of the zener diode and a second power terminal. The collector of the first transistor is connected to the one end of the zener diode to regulate the zener current and hence the zener voltage. A third transistor is coupled at its base to the one end of the zener and its emitter is connected to an output terminal to produce an output voltage which is a function of the zener voltage. The collector of the second transistor is connected to the emitter of the third transistor to pass a current through the third transistor which is approximately equal to the current through the first and second transistors whereby the base-to emitter junction of the third transistor and its temperature variations have little, if any, effect on the output voltage.

Abstract: An electronic substrate is provided in the form of a sintered body of polycrystalline alumina ceramic which further contains up to approximately 4% glass forming oxide selected from SiO.sub.2, MgO and ZrO.sub.2 along with about 0.4-2.0% refractory metal oxide to substantially reduce visible transmission in said substrate. In a preferred embodiment, said substrate comprises an elongated member of the ceramic material such as a flat layer which further includes a central cavity region housing an integrated circuit component such as a chip in which may be further provided with cover means for the central cavity in said member that can be formed with the same ceramic.

Abstract: A method for using a self-aligned electromigration barrier metal and flow oxidation mask utilizing titanium nitride as the preferred embodiment. After providing a metallic mask layer, contact openings in a semiconductor substrate are sputtered with suitable metal (in the preferred embodiment, titanium) in a suitable atmosphere (in the present embodiment, nitrogen) to deposit a thin layer of material at the exposed junction sites. This deposited material serves as a barrier to spiking with an overlying metallic interconnect layer, improves contact adherence, and serves as an oxidation mask during subsequent high temperature flow processing steps. The metallic mask layer is removed, and optionally an interlevel oxide layer is flowed to provide a better contact between a subsequent metallic interconnect level and the barrier metal/oxidation mask material. After any flow step, a metallic contact layer may be formed to the silicon junction through the barrier metal/oxidation mask material.

Abstract: Nonuniform topographical features on a substrate are effectively coated for lithographic processing by spin-coating with a suitable resin material in a dual spin cycle. The coating material is initially spin-coated onto the substrate at not less than 4000 rpm, preferably from 6000 to 8000 rpm, until build-up of the coating is detectable on a side wall of a topographical feature facing the centrifugal center of the spinning substrate. The spin speed is immediately reduced to less than 4000 rpm, preferably from about 1000 to 3500 rpm, and spinning is continued for a time sufficient to dry the coating. The subject process is particularly suitable for coating a substrate having nonuniform topographical features with a planarizing material.

Abstract: A test mask is provided for determining that an automatic IC photomask testing machine is scanning within a desired die area. The test mask includes a plurality of care areas which correspond to the die areas of a mask to be tested. The peripheral region surrounding each care area includes portions which may be opaque and portions which may be transparent. These opaque and transparent portions are arranged so that when two care areas are being scanned and the scan improperly leaves the care area and enters the peripheral region, the portion of the peripheral region of the one care area being scanned is opaque while the portion of the peripheral region of the other care area is transparent. This will be interpreted by the mask testing machine as an error and will therefor be indicative that the machine will scan outside of the desired die areas when testing an IC photomask.

Abstract: An apparatus and method are disclosed for replenishing the depleted component of a multicomponent etching solution. A portion of the etching solution is analyzed with a UV detector to determine the concentration of the depleted component. An output signal is produced by the UV detector which is a function of the depleted component's concentration. In response to this output signal, a microprocessor is used to control the amount of make-up solution, enriched with the depleted component of the multicomponent etching solution, which is added to the etching solution. With the use of this system, a substantially uniform etch bath composition is maintained.

Abstract: A high frequency CMOS voltage level shifter providing either an inverted or noninverted signal output shifted in voltage level from an input signal. The level shifter includes two pairs of metal oxide semiconductor transistors with the transistors of each pair connected together and respectively connected to a first and second voltage source. The gates of a transistor in each pair are cross connected to the interconnected drains of the opposing transistor pair. First and second conducting elements are respectively connected to the cross connected transistor gates to discharge a transient capacitive gate charge present during output signal voltage level shifting.

Abstract: Tapered openings are formed in silicon oxide layers on a substrate by first saturating the silicon oxide layers with water, such as by immersing the substrates and the silicon oxide layers in water. The silicon oxide layers are then heated to dehydrate them to a desired water content at which a desired adhesion of a resist layer to the silicon oxide layer is achieved. A photoresist layer is then coated on the silicon oxide layers and photolithographically defined to provide them with openings therethrough over the area of the silicon oxide layers where the tapered openings are to be provided. The exposed area of the silicon oxide layers are then etched with an etchant for silicon oxide, such as buffered hydrofluoric acid, containing a component for lifting the edge of the resist from the silicon oxide, such as an acid, to etch tapered openings through the silicon oxide layers.

Abstract: Each one of two switching transistors, driven by complementary input signals, has its conduction path connected between a different one of two output terminals and a first point of potential. Connected between each output terminal and a second point of potential are the conduction paths of a load transistor responsive to the signal at the other output terminal. A source follower transistor is connected to each output terminal. When the switching transistor connected to one output terminal is being turned-OFF, the source follower connected to that output terminal is turned-ON to enhance the voltage response at that terminal and to thereby accelerate the speed of response of the circuit and minimize its power dissipation.

Abstract: A timing system which includes a timer circuit, a source of first clock pulses for advancing the timer circuit, and a circuit for reading out the timer circuit in synchronism advanced therewith and where there is also included a second source of clock pulses asynchronous with respect to the first source of clock pulses, a synchronizing circuit is provided for storing an indication of the receipt of each second clock source pulse. Then the timer is advanced only when a pulse is produced by the first clock source and the indication is present that a signal has been produced by the second clock source.

Abstract: A high current lateral transistor for an integrated circuit device is disclosed. The emitter and collector regions extend into the base region for a distance of approximately one half the thickness of the base region. A second region of the same conductivity type as the collector, surrounds the collector and is spaced therefrom. The base contact shorts together this second region and the base region so that when the transistor goes into saturation excess current will not flow into the substrate.

Abstract: A power supply regulator in which a control pulse is generated at a position in time which varies in accordance with the voltage or current supplied by the power supply. The control pulse can be fed back across an isolation boundary with a simple device such as a pulse transformer with little or no loss of accuracy. Such a control signal is particularly adaptable to varying the duty cycles of transistor switch drive signals for switched-mode power supplies.