Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the tank servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

Abstract: An optical flying spot scanner having a lens array positioned between a scan line and a detector array and inclined at an angle to the axis of the scan line. Each of the lenses of the lens array has a coordinate position in a plane parallel to the scan line related to a particular segment of the scan line such that the information content of each segment of the scan line is transmitted to a different one of the tiered detectors of the detector array.

Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.