Patents Represented by Attorney, Agent or Law Firm Salzman & Levy
  • Patent number: 6614886
    Abstract: The present invention features a method for providing status information to a client based on data residing in an electronic database or e-file. The database of the information is maintained and updated, and is periodically analyzed to determine whether at least a portion of the data has changed since the last analysis or communication. If so, the client is automatically informed by the system, which initiates an automatic voice response (AVR) call out to the client. The client verifies that he or she is the true intended recipient of the status information before it is communicated. A log of this communication is also maintained by the system. The client has the opportunity to respond to the system AVR call and/or correct or provide additional information, the client voice response being stored in an appropriate voice mailbox.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: September 2, 2003
    Inventor: Lee Knox
  • Patent number: 6602989
    Abstract: The detection of gallium in biological samples is required due to its role in the diagnosis of tumor and for possible treatment of malignancies. However, the use of purely instrumental techniques is unsuitable for detection of low levels of gallium in biological matrices. New protein conjugates have been synthesized based on 4-(2-pyridylazo) ligands. The conjugates detect gallium in biological matrices using a non antibody-based sandwich assay format. The recovery level is between 97-101.3 with a relative standard deviation of less than 5%. The assay results in a detection limit of 5×10−8 M and a remarkable selectivity for gallium(III) relative to other metals investigated. The new method provides adequate accuracy for gallium applicable for animal physiology and clinical toxicology.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: August 5, 2003
    Assignee: The Research Foundation of State University of New York
    Inventors: Omowunmi A. Sadik, Hongwu Xu
  • Patent number: 6602170
    Abstract: A torso exercising apparatus and system for performing various calisthenics and maneuvers to tone and build the body. Right and left handles of the apparatus are disposed between two respective pairs of spaced-apart, front and rear rollers. Each of the roller pairs is affixed to a base. The handles are each disposed on a diagonal with respect to their respective front and rear roller pairs. The diagonally oriented handles eliminate wrist strain and have a further advantage of facilitating sideways movement.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: August 5, 2003
    Inventor: Dragan Z. Ilic
  • Patent number: 6594914
    Abstract: A blade squaring gauge for ice skates is in the form of a small, hand-held disk having the approximate size of a silver dollar. Along the circumferential edge of the disk are slots for truing the edges of the blade. Each slot corresponds to a different arc or curvature of the edge of the blade and provides squareness measurement at that position. A blade can be fitted into a given slot corresponding to the particular curvature on the peripheral blade surface and the squareness of the inner and outer edges of the blade is determined. The gauge eliminates the guesswork in determining trueness of the edge for given blade curvatures along the periphery of the blade.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 22, 2003
    Inventor: Kevin Babcock
  • Patent number: 6597062
    Abstract: The present invention is a family of memory modules. In one embodiment a memory module with granularity, upgradeability, and high throughput of at least 4.2 gigabytes per second using two channels of RAMBUS memory devices in a typical volume of just 2.2 inches by 1.1 inches by 0.39 inch. Each module includes an impedance-controlled substrate having contact pads, memory devices and other components, including optional driver line terminators, on its surfaces. The inclusion of spaced, multiple area array interconnections allows a row of memory devices to be serially mounted between each of the area array interconnections, thereby minimizing the interconnect lengths and facilitating matching of interconnect lengths. Short area array interconnections, including BGA, PGA, and LGA options or interchangeable alternative connectors provide interconnections between the modules and the rest of the system.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: July 22, 2003
    Assignee: High Connection Density, Inc.
    Inventors: Che-yu Li, Sharon L. Moriarty
  • Patent number: 6596597
    Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma
  • Patent number: 6590159
    Abstract: The present invention provides an electronic package for high speed, high performance semiconductors. It includes a plurality of devices, circuit members and short interconnections between the circuit members for maintaining high electrical performance. Suitable applications requiring high speed, impedance-controlled transmission line buses throughout the entire package include microprocessor and digital signal processor data buses, and high speed memory buses for products such as laptop and handheld computing and telecommunications devices. Circuit members include printed circuit boards and circuit modules, and may be formed from a wide variety of materials with unpacked or packed semiconductors attached directly to the circuit members. Through the use of clamps the package is at least factory reworkable and can be field separable. Thermal management structures may be included to maintain the high density devices within a reliable range of operating temperatures.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: July 8, 2003
    Assignee: High Connection Density, Inc.
    Inventors: Zhineng Fan, Ai D. Le, Che-Yu Li
  • Patent number: 6578985
    Abstract: The present invention features a system for uniformly distributing luminance and a high degree of collimation from a back light module for flat-panel, liquid crystal displays (LCDs) simultaneously. A constant and uniform luminance output of the back light module in two directions is obtained through appropriate selection of lamps, geometry and optical components. An appropriate balance of lamps, lamp spacing, diffusers and light collimating optics are chosen to produce a high brightness back light module with very high intensity output over two very large surfaces. Variations in intensity over the illuminated area are minimized using light recycling in conjunction with the reflective diffusers and collimating optics. Precision collimators eliminate light beyond a defined angle, as required in tiled or monolithic flat-panel LCDs with predetermined display specifications.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: June 17, 2003
    Assignee: Rainbow Displays, Inc.
    Inventors: Donald P. Seraphim, Dean W. Skinner
  • Patent number: 6572068
    Abstract: A collapsing tree stand having a compact construction with an improved center of gravity and elongated folding legs. The legs of the tree stand are each broadened in width at their fold-up pivot point and then tapered to a narrower width at their distal ends. This taper provides an improved center of gravity about the base, thus reducing the tendency of the tree to tip over. The legs are sufficiently elongated to provide good balance in their extended position.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: June 3, 2003
    Assignee: Polytree (Hong Kong) Co. Ltd.
    Inventor: Cheng Chung Wai
  • Patent number: 6570259
    Abstract: The present invention provides a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: David J. Alcoe, Eric A. Johnson, Matthew M. Reiss, Charles G. Woychik
  • Patent number: 6567138
    Abstract: This invention describes fabrication techniques for producing microdisplays suitable for combining into tiled, flat-panel displays having visually imperceptible seams. Assembly techniques to overcome flatness requirements imposed by tiled, flat-panel display assemblies are also described. Edge treatment techniques for individual microdisplays while still part of the silicon die or wafer are also described. The use of these inventive techniques allows the assembly microdisplays into tiled, flat-panel that are appear visually seamless and optically uniform.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: May 20, 2003
    Assignee: Rainbow Displays, Inc.
    Inventors: J. Peter Krusius, Donald P. Seraphim
  • Patent number: 6561722
    Abstract: A load bearing structural joint that is fabricated using an electromagnetic process, features a tube that is joined to a fitting of another component. Lightweight materials and thicknesses can be used, because the welding is performed without the adverse effects of annealing or heat. The fabricated structure has an improved strength to weight ratio, and prolonged fatigue life.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 13, 2003
    Assignees: Fuel Cell Components and Integrators, Inc., Inli, LLC, Tabco Technologies, Inc.
    Inventors: Danylo Dudko, Viacheslav Shevchenko, Ludmilla Kistersky, Thomas A. Barber, Robert L. Benoit, Bernard I. Rachowitz, Glenn L. Spacht, Anthony Mascolo
  • Patent number: 6557252
    Abstract: A method and apparatus for fabricating uniform splices for stranded cables. A joint for a stranded cable can be formed by inserting the ends of two cables into an electrically conductive splice band which, in turn, is inserted into a coil or inductor. The splice is fabricated by a process known as magnetic pulse forming, or magnetic pulse welding wherein a very large electrical current of short duration is directed through the coil or inductor from a charged capacitor bank. The resulting magnetic field in the coil or inductor induces a magnetic field on the splice band, compressing the splice band uniformly around the circumference of the two cable ends being spliced. In the case of magnetic pulse welding, the splice not only uniformly compresses the stranded cables, but a weld is also created between the inner diameter of the sleeve and the adjacent stranded cables.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: May 6, 2003
    Assignee: Fuel Cell Components and Integrators, Inc.
    Inventors: Richard A. Bennett, Robert L. Benoit, Bernard I. Rachowitz, Glenn L. Spacht
  • Patent number: 6555762
    Abstract: The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bernd K. Appelt, Jeffrey D. Gelorme, Sung Kwon Kang, Voya R. Markovich, Kostas Papathomas, Sampath Purushothaman
  • Patent number: 6554234
    Abstract: A device for assisting muscularly disadvantaged persons and hypotonic individuals to perform a multiplicity of tasks. The device includes a hand grip and wrist support that is supported along two dimensions of travel by frictionless support surfaces, such that the task is performed with a gliding or fluid movement.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: April 29, 2003
    Inventor: Howard P. Holdren
  • Patent number: 6556261
    Abstract: This invention describes fabrication techniques for producing microdisplays suitable for combining into tiled, flat-panel displays having visually imperceptible seams. Assembly techniques to overcome flatness requirements imposed by tiled, flat-panel display assemblies are also described. Edge treatment techniques for individual microdisplays while still part of the silicon die or wafer are also described. The use of these inventive techniques allows the assembly microdisplays into tiled, flat-panel that are appear visually seamless and optically uniform.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: April 29, 2003
    Assignee: Rainbow Displays, Inc.
    Inventors: J. Peter Krusius, Donald P. Seraphim
  • Patent number: 6550276
    Abstract: An article of jewelry with ornamental male and female inserts that are reversible relative to their frame. The inserts form an opening on top to accept wire from a balled wire attached to the tubing on the frame. The balled wire allows the inserts to be flipped easily, while a wire, passing through the tubing, is the axis of rotation. A spring wire is attached to the bottom of the frame and fits into a notch formed by the mating inserts to secure the inserts in place. A stop is positioned on the back of the frame to prevent the inserts from extending beyond the back of the frame.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: April 22, 2003
    Inventor: Alan J. Frank
  • Patent number: 6546625
    Abstract: The present invention provides a process for forming a contact member cable. The cable is a longer version of a contact member and can then be cut into shorter, individual contact members, to meet the particular requirements for a specific connector application. The contact members can be used as the conductive elements for a family of land grid array connectors that provide, among other things, a low profile, uniform electrical and mechanical performance, and reworkability if a contact member is damaged. The connectors are intended to interconnect electrical circuit members such as printed circuit boards, circuit modules, or the like. Such circuit members may be used in information handling system (computer) or telecommunications environments.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 15, 2003
    Assignee: High Connection Density, Inc.
    Inventors: Ai D. Le, John G. S. Lahlouh, Zhineng Fan, Matti A. Korhonen, John D. Williams
  • Patent number: 6545895
    Abstract: The present invention is a family of memory modules. In one embodiment a memory module with granularity, upgradability, and a capacity of two gigabytes uses 256 MB SDRAM or DDR SDRAM memory devices in CSPs in a volume of just 4.54 inches by 2.83 inches by 0.39 inch. Each module includes an impedance-controlled substrate having contact pads, memory devices, and other components, including optional driver line terminators, on its surfaces. The inclusion of spaced, multiple area array interconnections allows memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating the matching of interconnect lengths. Short area array interconnections, including BGA, PGA, and LGA options or interchangeable alternative connectors provide interconnections between the modules and the rest of the system. Thermal control structures may be included to maintain the memory devices within a reliable range of operating temperatures.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: April 8, 2003
    Assignee: High Connection Density, Inc.
    Inventors: Che-yu Li, Sharon L. Moriarty
  • Patent number: 6540525
    Abstract: The present invention is a cost effective module that provides high performance, high density and highly reliability interconnections needed between the various circuit devices that form a functional system or a part of a larger system. It includes circuit members having high speed, impedance-controlled transmission line signal paths, short land grid array interconnections between circuit members and, optionally, driver line terminators built into one of the circuit members, for maintaining high electrical performance. Suitable applications include mainframe computers, workstations, telecommunications networks, or other electronic equipment. The circuit members may be formed on conventional printed circuit cards with unpacked or packed circuit devices attached directly to the circuit members. Thermal control structures may be included to maintain the circuit devices within a reliable range of operating temperatures. A clamp is also included.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: April 1, 2003
    Assignee: High Connection Density, Inc.
    Inventors: Che-Yu Li, David A. Lysack, Brian D. Harry, John J. Kresse