Abstract: Methods and apparatuses for transformer signal coupling for flip-chip circuit assemblies are presented. A device for coupling dies in flip-chip circuit assembly may include a first die associated with a first fabrication process and a first inductor physically coupled to the first die, where the first inductor receives an RF input signal. The device may further include a second die associated with a second fabrication process, and a second inductor physically coupled to the second die, where the second inductor is positioned so the first inductor can inductively couple the RF signal in the second inductor. A method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer.

Abstract: Methods and apparatus for improved beacon signaling in a wireless communication system are described. Information is encoded in the tone position of the beacon tone. The information encoded may include sector type, sector index and slope index, as well as some time index. The information is coded in the tone position so that any few of several beacons can be decoded in order to decode the information. The methods and apparatus described in the invention improve the robustness against frequency selective fading and do not require wireless terminals to establish synchronization for reliable base station detection.

Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract: A multi-mode base station includes a transmit standby mode and an active mode. Transmit standby mode of base station operation is a low power/low interference level of operation as compared to active mode. In transmit standby mode at least some of the synchronization signaling such as pilot tone signaling is reduced in power level and/or rate with respect to the active mode. In transmit standby mode, the base station has no active state registered wireless terminals being serviced but may have some sleep state registered wireless terminals being serviced. Mode transitions from active to transmit standby may be in response to: a detected period of inactivity, scheduling information, base station mode change signals, and/or detected wireless terminal state transition. Mode transitions from transmit standby to active may be in response to: scheduling information, access signals, wake-up signals, hand-off signals, wireless terminal state change signals, and/or base station mode change signals.

Abstract: A first device is configured to select and utilize a connection identifier (CID) for a peer-to-peer communication connection between the first device and a second device in a wireless communications network. The CID is selected from a predetermined set of a plurality of CIDs. Prior to selecting the connection identifier, the first device monitors a CID broadcast channel to determine whether the CID is being utilized by other nearby connections. If it is determined that the CID is being utilized by another connection in the proximity, a different (unused) CID is selected. A transmission request is transmitted to the second device using a first transmission resource unit within a traffic management channel slot, the first transmission resource unit being determined as a function of the selected CID. The first device transmits traffic data to the second device in a traffic channel slot corresponding to the traffic management channel slot.

Abstract: Techniques for using at least one of omni-directional and directional antennas for communication are described. A station may be equipped antenna elements selectable for use as an omni-directional antenna or one or more directional antennas. The station may select the omni-directional antenna or a directional antenna for use for communication based on various factors such as, e.g., whether the location or direction of a target station for communication is known, whether control frames or data frames are being exchanged, etc.

Abstract: A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit.

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract: Methods and apparatus are described for improved utilization of air link resources. A base station includes at least one of a plurality of receive antenna elements and a plurality of transmit antenna elements for communicating with a wireless terminal. The base station generates channel estimation vectors corresponding to wireless terminals using the base station, where a generated channel estimation vector includes different elements corresponding to different base station antenna elements. The base station determines a level of orthogonality between pairs of channel estimation vectors corresponding to different wireless terminals. At least some of the segments to be assigned by the base station are substantially overlapping, e.g., the segments overlap fully or to a high degree.

Abstract: A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a redistribution layer with a first electrical terminal coupled to the plurality of circuit components by a first through-silicon via, and a second through-silicon via electrically coupled to a third through-silicon via by a trace on the back side redistribution layer. Also, disclosed is a method of coupling circuit components on a die using through-silicon vias and a back side redistribution layer.

Abstract: Wireless platform attitude information such as pitch, roll and heading are disclosed. Attitude estimates can be made by using orthogonally mounted gyroscopes. Attitude estimates can be also made by determining the direction of arrival of signals and comparing the direction of arrival of the signals with the position of the transmitters and the position of the receiver. The attitude estimates can be then combined to determine “real time” attitude information.

Abstract: A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is configured to change a logic state of the storage element. A first and a second write driver with programmable drive strengths are coupled to the bit line and source line respectively to enable control of drive strengths of write operations to the storage element.

Abstract: A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element.

Abstract: A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Abstract: A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.

Abstract: A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.

Abstract: One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other.

Abstract: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Abstract: A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.