Patents Represented by Attorney Samsung Electronics Co., Ltd.
  • Patent number: 8154467
    Abstract: Disclosed is an antenna apparatus which can control directivity of a plurality of radiation elements using one parasitic element. The antenna apparatus includes two radiation elements arranged on a base parallel to each other, and a parasitic element disposed between the two radiation elements. Radiation directivity of the two radiation elements is controlled according to the length of the parasitic element. This configuration provides a small-sized antenna apparatus including a plurality of radiators with desired directivity.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: April 10, 2012
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Tsutomu Mitsui
  • Patent number: 7693347
    Abstract: Methods and apparatus to measure small shifts and rotations of video images captured in short succession after a first reference video image is captured, and to add the sequence of captures while shifting or rotating back the shifted or rotated images, in order to improve the SNR in low light conditions.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eugene Fainstain, Yoav Lavi
  • Patent number: 6093605
    Abstract: A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 25, 2000
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Kyong-moo Mang, Jung-dal Choi
  • Patent number: 6023306
    Abstract: NTSC interference detectors include an NTSC extracting filter for supplying an NTSC extracting filter response that separates accompanying co-channel interfering NTSC signal component from the received I-channel baseband signal and its direct bias component. The NTSC extracting filter comprises a comb filter, which includes a delay circuit for supplying in response to said received I-channel baseband signal differentially delayed signals with a prescribed amount of differential delay equal to the duration of an even number of horizontal scanning periods of NTSC signal as will generate said co-channel interfering NTSC signal components. The comb filter further includes a subtractor for differentially combining the differentially delayed signals to generate the comb filter response.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: February 8, 2000
    Assignee: Samsung Electronics Co. Ltd.
    Inventor: Allen LeRoy Limberg
  • Patent number: 5982457
    Abstract: Radio receivers for receiving DTV signals, in accordance with the Advanced Television Systems Committee (ATSC) standard, or analog TV, in accordance with the National Television Sub-Committee (NTSC) standard, each use a single first detector for both types of signal. This single first detector supplies its output signals to an intermediate-frequency amplifier chain for TV signals and to another intermediate-frequency amplifier chain for analog TV signals. The response of the IF amplifier chain for DTV signals is synchrodyned to baseband, supplied to symbol decoding circuitry, and used by first automatic gain control circuitry to develop AGC for amplifier stages in that IF amplifier chain when DTV signals are received.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: November 9, 1999
    Assignee: Samsung Electronics, Co. Ltd.
    Inventor: Allen LeRoy Limberg
  • Patent number: 5968840
    Abstract: The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory device is formed; forming a first insulating layer by isolation of electrical elements in order to divide an active region and a passive region; forming and patterning a first conductive layer through a contact to which the active region and a capacitor are connected on the insulating layer to form a storage node; forming a dielectric layer of the capacitor on the storage node; forming and patterning a polysilicon layer on the dielectric layer to form a storage node; forming a second insulating layer on the plate node and planarizing the insulating layer by thermal treatment; forming a third conductive layer to a predetermined thickness on the planarized insulating layer; polishing and planarizing the third conductive layer by chemical-mechanical polishing techn
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: October 19, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyucharn Park, Yeseung Lee, Cheonsu Ban, Kyungwook Lee
  • Patent number: 5744374
    Abstract: A ferroelectric memory device of an MFIS FET structuring using a yttrium oxide film as a buffer film and a manufacturing method of the memory device are provided. The MFIS FET includes a p-type silicon substrate, a field oxide film formed in a device isolation region of the silicon substrate, a gate yttrium oxide film formed on the surface of the silicon substrate, a gate ferroelectric film formed on the gate yttrium oxide film, a gate TiN electrode formed on the gate ferroelectric film, and an n-type source/drain region formed in the silicon substrate of both sides of the gate TiN electrode. In this way, single crystals of the gate yttrium oxide film are easily formed resulting in the formation of a good-quality ferroelectric film on the yttrium oxide film.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: April 28, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Moon
  • Patent number: 5720846
    Abstract: A plasma etching system is disclosed that minimizes energy loss due to the dissipation of plasma, maintaining high plasma density, and thus increasing ionization efficiency. By this construction, wafers may be etched under low pressure, which reduces the chance of impact applied to the wafers and increases the productivity of the etching system. The construction has a chamber casing having a plasma chamber into which plasma for etching wafers is injected, a reflective film coated on the outer surface of the chamber casing, the reflection film acting to insulate the plasma chamber and prevent the plasma from leaking out of the plasma chamber, and a coil wound around the chamber casing over the reflective film. A predetermined voltage is applied to the coil to generate plasma in the plasma chamber.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: February 24, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Whikun Yi
  • Patent number: 5700603
    Abstract: In a mask for X-ray lithography and a method for manufacturing the same, a mask pattern is formed on a first silicon substrate and then an intermediate material is coated on the mask pattern in order to protect the mask pattern and further the intermediate material of the first silicon substrate is stuck on a second silicon substrate where a membrane is to be formed. Next, the second silicon substrate is thinned by methods of grinding and polishing. Here, thickness of the membrane can be controlled depending on an etching amount in unit of grinding and polishing. Therefore, since the membrane is formed after the mask pattern has been formed, not only transformation of the mask pattern generated from a process of mask pattern and breakage of the mask pattern can be prevented but also thickness of the mask pattern can be controlled as desired.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: December 23, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-hun Lee
  • Patent number: 5698882
    Abstract: In an LDD polysilicon thin-film transistor, the active layer is formed in a single body and the upper surface thereof is oxidized. A gate insulating layer has a bird's beak type structure and the source and drain region are simultaneously formed in high and low concentrations by performing one ion implantation process, so that the manufacturing process is simplified and the quality of the active layer is improved. Also, the ion concentration level tapers off toward the channel, so that the V.sub.gs -I.sub.ds characteristic is improved.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: December 16, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-hae Park