Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: Methods, systems, and media to enhance memory leakage management by identifying a suspect allocation pattern during execution of a task, which may be indicative of memory leakage and implementing measures to protect against memory leakage based upon the suspect allocation pattern, are disclosed. More specifically, embodiments may detect a suspect allocation pattern by monitoring memory allocations and deallocations for tasks. The pattern of memory allocations and deallocations may then be analyzed to determine whether a suspect allocation pattern exists. For instance, the memory allocations and deallocations may be compared to determine whether there is an increasing net residual allocation left by the task after it has reached a quiescent runtime state. In some embodiments, a suspect allocation pattern exists if the total memory allocation for a task continues to rise after a pre-determined time period.