Abstract: The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA?VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy?Iz and generates currents IA and IB by minimizing this difference.

Abstract: A method and apparatus for improving speed measurement quality in systems having multi-pole machines is taught. The method compensates for pole misalignment by computing speed based upon moving average techniques. In one embodiment, a moving average speed averaged over a complete interval of rotation is determined, based upon measurements of one or more magnetic pole position sensors for magnetic pole location. In another embodiment, a time interval between two poles is averaged over one or more rotational periods, and the average time interval is used to determine the moving average speed. Computation of the moving average speed reduces errors in speed measurements due to pole misalignment and may provide for smaller control adjustment times for controlling motor speed variability. In one embodiment, the speed measurement system includes a multi-pole rotor, and a controller having a capture timer and a buffer.

Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.