Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.
Type:
Grant
Filed:
August 12, 1996
Date of Patent:
March 23, 1999
Assignee:
Data General Corporation
Inventors:
William F. Baxter, Robert G. Gelinas, James M. Guyer, Dan R. Huck, Michael F. Hunt, David L. Keating, Jeff S. Kimmell, Phil J. Roux, Liz M. Truebenbach, Rob P. Valentine, Pat J. Weiler, Joseph Cox, Barry E. Gillott, Andrea Heyda, Rob J. Pike, Tom V. Radogna, Art A. Sherman, Michael Sporer, Doug J. Tucker, Simon N. Yeung