Abstract: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

Abstract: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.

Abstract: A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.

Abstract: The present invention relates to methodologies for the self-assembly of nanoparticles onto a release support that is capable of covalent integration into flexible free-standing films. Such films display usefull constitutive properties, such as permittivity, permeability, electrical conductivity, thermal conductivity, and nonlinear optic properties. The type of property is dependant upon the type of nanoparticle incorporated into the compliant polymeric matrix. The compliant matrix may be any material that reacts with the components in the nanoparticle film and may be separated from the release substrate. The nanoparticles may be dispersed uniformly or spatially patterned throughout the self-assembled film.

Abstract: Embodiments relate to a method of manufacturing a semiconductor device.

Abstract: A method of forming a transistor reduces leakage current and hot carrier effects, and therefore improves current performance. The method of forming a transistor includes selectively etching the semiconductor substrate to form a substrate protrusion and expose a buried source/drain implant region. A gate insulating layer covers the substrate protrusion and the first source/drain region. A gate conductor layer is selectively etched to form a gate pattern covering the sidewalls of the substrate protrusion and a portion of the semiconductor substrate adjacent to the sidewalls of the substrate protrusion. A second source/drain region is stacked over the top of the substrate protrusion. Contacts connected to the gate pattern and the first and second source/drain regions.

Abstract: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Abstract: A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing a semiconductor device that may be capable of improving a step coverage of main chip and scribe lane regions during a formation of an interlayer dielectric are provided. In embodiments, the semiconductor device may include metal layers formed on a substrate including a main chip region and a scribe lane region, respectively, an interlayer dielectric formed on the substrate including the metal layers, a step coverage improving layer formed on an interlayer dielectric of the scribe lane region, a via hole inside the step coverage improving layer and the interlayer dielectric, and a via plug formed by filling the via hole with a metal.

Abstract: A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor includes the steps of forming a lower electrode of a first polysilicon layer over a semiconductor substrate, forming a dielectric layer over the lower electrode, forming a second polysilicon layer over the dielectric layer, patterning the second polysilicon layer, implanting impurities into a side wall of the patterns of the second polysilicon layer and selectively etching the side wall of the patterns of the second polysilicon layer. The impurities are implanted to control an effective line width of the patterns of the second polysilicon layer as an upper electrode.

Abstract: A method for fabricating a fin FET in a semiconductor device. The method includes sequentially depositing first and second insulation films on a semiconductor substrate, etching the first and second insulation films using a first mask to form a trench, and depositing a first conductor in the trench.

Abstract: A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide and a floating gate are formed only in a portion where injection of electrons occurs and a gate insulation film is formed on a semiconductor substrate between two portions of the tunneling oxide.

Abstract: The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.

Abstract: The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer.

Abstract: In accordance with embodiments, viewable images can be created in glass. Viewable images may be created in glass by using a projector which projects ultraviolet light to excite light emitting material. Clear images may be created in glass because the size the light emitting particles in the glass is less than 400 nanometers. In embodiments, the visible illumination of a transparent substrate to display an image is possible, while the transparent substrate remains transparent. Accordingly, for example, drivers of automobiles may view images (e.g. map images) on their windshield while they are driving. As another example, window shoppers may view enhanced advertisements in the windows of stores that they are approaching.

Abstract: The present invention provides a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography, which enhances electrical characteristics of the device, and which facilitates a cell size reduction. The present invention includes forming a mask defining a trench forming area on a semiconductor substrate, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the mask, forming a device isolation layer filling up the trench to maintain an effective isolation layer thickness exceeding a predefined thickness, removing the mask, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate including the conductor patterns.

Abstract: In accordance with embodiments, viewable imagines can be created in glass. Viewable images may be created in or on glass (or other at least partially transparent substrate), by using microstructures to scatter light from a projector, while the glass maintains transparent or translucent properties. In embodiments, the microstructures are integrated into glass in patterns.

Abstract: A system and a method of a transparent color image display utilizing fluorescence conversion (FC) of nano-particles and molecules are disclosed. In one preferred embodiment, a color image display system consists of a light source equipped with two-dimensional scanning hardware and a FC display screen board. The FC display screen board consists of a transparent fluorescence display layer, a wavelength filtering coating, and an absorption substrate. In another preferred embodiment, two mechanisms of light excitation are utilized. One of the excitation mechanisms is up-conversion where excitation light wavelength is longer than fluorescence wavelength. The second mechanism is down-conversion where excitation wavelength is shorter than fluorescence wavelength. A host of preferred fluorescence materials for the FC screen are also disclosed. These materials fall into four categories: inorganic nanometer sized phosphors; organic molecules and dyes; semiconductor based nano particles; and organometallic molecules.

Abstract: A wheel transmission for a heavy construction vehicle, which can be applied to specially-equipped vehicles as well as heavy construction vehicles such as a forklift truck and a mechanical shovel. The wheel transmission (200) is intended to drive a pair of right and left wheels independently, and includes a planetary gear assembly (210), a change clutch part (230), a one-way clutch part (300), and a brake part (270) housed in an axle hub at which opposite ends of a drive axle shaft are located, turning force from an engine of a heavy construction vehicle being transferred to the drive axle shaft through a torque converter, a driving shaft, a final reduction gear and a differential gear.