Abstract: A CMOS image sensor and fabricating method thereof by which capacitance of a floating diffusion region (FD) can be increased.

Abstract: An image sensor according to embodiments may include a semiconductor substrate, photodiodes disposed over the semiconductor substrate, a dielectric layer formed over the photodiodes, a color filter layer formed over the dielectric layer, a planarization layer formed over the color filter layer, a phase change material formed over the planarization layer, and a plurality of microlenses formed over the planarization layer, wherein the phase change material is positioned in the microlens. Further, a method for manufacturing an image sensor according to embodiments may include forming a dielectric layer over a semiconductor substrate with a plurality of photodiodes, sequentially forming a color filter layer and a planarization layer over the dielectric layer, forming a phase change material over the planarization layer, forming a patterned phase change material by partially etching the phase change material, and forming microlenses over the planarization layer and the phase change material.

Abstract: A flash memory includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active region, a deep implant region formed at a lower portion of the shallow trench isolation and the active region between the stacked gates and a shallow implant region formed at a surface of the active region between the stacked gates.

Abstract: Disclosed is a semiconductor package pickup apparatus. The apparatus includes a picker base formed with first and second main feeding holes, which are connected to each pneumatic line providing a pneumatic pressure and aligned in a dual-layer structure, and an adsorption pad coupled to a lower portion of the picker base and formed with adsorption holes connected to the first and second main feeding holes. The pneumatic pressure supplied into the first and second main feeding holes is independently controlled, so that the apparatus easily loads or picks up semiconductor packages, even if the size of the semiconductor packages becomes reduced.

Abstract: Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device and a manufacturing method thereof that can reduce RC delay within the semiconductor device. Embodiments provide a semiconductor device including: a first interlayer dielectric layer formed over the a semiconductor substrate, a first metal wire and a second metal wire formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first and second metal wires, and a phase change material layer formed between the first and second metal wires.

Abstract: Provided are an apparatus and method for transmitting and receiving data bits. The apparatus includes a transmitter configured to generate a transmission signal corresponding to the data bits and having a periodic transition, a data line configured to transmit the generated transmission signal, and a receiver configured to generate a reception clock signal from the periodic transition of the transmission signal (“reception signal”) transmitted through the data line, sample the reception signal according to the generated reception clock signal to recover the data bits. Accordingly, it is possible to transmit clock information without a clock line separate from the data line.

Abstract: A mask for forming a metal line and a via contact, and a method for fabricating a semiconductor device using the same, minimizes misalignment. The mask includes a first mask region having a dark tone for light shading, a second mask region having a half tone, being disposed within the first mask region to form the metal line, and a third mask region having a clear tone, being disposed within the second mask region to form the via contact.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a second isolation layer over a first well region between first and third isolation layers. A semiconductor device may include a gate over a second isolation layer. A semiconductor device may include a second well region over a first well region between a third isolation layer and a gate, a first ion-implanted region over a second well region between a third isolation layer and a gate, and/or a second ion-implanted region between a first ion-implanted region and a gate. A semiconductor device may include an accumulation channel between a second well region and a gate.

Abstract: A platinum-based nano catalyst supported carbon nano tube electrode and a manufacturing method thereof, more particularly to a manufacturing method of a carbon nano tube electrode and a carbon nano tube electrode supported with the platinum-based catalyst by growing the carbon nano tube on the surface of the carbon paper and using a CVD method on the surface of the carbon nano tube. By growing the carbon nano tube directly, the broad surface area and excellent electric conductivity of the carbon nano tube can be utilized maximally, and especially, the nano catalyst particles with minute sizes on the surface of the carbon nano tube by using the CVD method as a supporting method of the platinum-based catalyst on the surface of the carbon nano tube, the amount of the platinum can be minimized and still shows an efficient catalyst effect and by improving the catalyst activity by increasing the distribution, so academic and industrial application in the future is highly expected.

Abstract: A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master.

Abstract: Porous microperforators (210A), preferably in an array of multiple perforators are employed for delivery of a drug, where the micro-perforators may dissolve in situ. Suitable micro-perforators may include multiple layers of dissolvable materials to effect sequential drug delivery. In further aspects, contemplated micro-perforators may employ a diagnostic device in which a detector layer or detector is operationally coupled to the micro-perforators.

Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, and/or an isolation layer. An isolation layer may include a predetermined area formed over a reduced surface field region, may be partially overlapped with a top surface of a substrate and/or may include an area formed adjacent a high voltage well. A low voltage well may be formed over a substrate. A gate electrode may extend from a predetermined top surface of a body region to a predetermined top surface of an isolation layer. A drain region may be formed over a low voltage well. A source region may be formed over a body region and may have at least a portion formed under a gate electrode.

Abstract: A slope compensation circuit includes an oscillator for generating a first clock signal having a reference frequency, a ramp signal generator for generating a ramp signal having a duty ratio of about 50% or higher based on the first clock signal, and a slope compensation signal generator for outputting a slope compensation current based on the ramp signal.

Abstract: Disclosed herein is an ejector for an injection molding machine used to extract a molded product formed inside a die, the ejector including: a first ejector plate which is movably installed in a moving plate for fixing the die; a second ejector plate which is separably connected to the first ejector plate; and an ejector pin which is installed in at least one of the first and second ejector plates so as to push outward the molded product.

Abstract: A beam switching antenna method and apparatus for controlling a beam switching antenna system including an antenna element for forming a beam, at least one conductive reflector for reflecting the beam, and a ground switch for applying a reference voltage to the least one conductive reflector, the method including selectively configuring the beam switching antenna system for a current-directional beam pattern to receive a first signal and for a non-directional beam pattern to receive a second signal; comprising the first and second signals; and controlling, using the ground switch; the beam based on the comparison of the first and second switching.

Abstract: A boot strap driver including a fast differential level shifter are disclosed. The fast differential level shifter may include a first differential amplifier differentially amplifying a pulse width modulation signal and an inverted pulse width modulation signal and outputting a first differential amplification voltage and a second differential amplification voltage based on the amplified result. The fast differential level shifter may also include a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage, and shifting the differential amplification voltages to voltages having an output range between a first voltage and a second voltage based on the amplified result.

Abstract: A method for forming a metal electrode of a system in package of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer having high viscosity at a lower portion of the through hole in order to seal the lower portion thereof, and forming a through electrode by filling copper in the through hole. There is an effect of efficiently forming a through electrode having a large depth corresponding to the height of stacked semiconductor devices in the system in package. Filling copper in a through hole having a large depth-to-width ratio may be efficiently done by OSP coating, electrolysis copper plating, and electro Cu plating processes.

Abstract: A method for forming an interlayer insulating film includes providing a semiconductor substrate having a first substrate region with a plurality of metal wiring and a second substrate region having no metal wiring, and then forming an insulating film dummy pattern in the second substrate region, wherein the insulating film dummy pattern has the same thickness as the metal wiring, and then forming an interlayer insulating film over the semiconductor substrate including the insulating film dummy pattern.

Abstract: A method for forming copper wirings in a semiconductor device may include depositing a lower insulating film over a semiconductor substrate; forming vias in the lower insulating film; depositing tungsten over the entire surface of upper portion of the lower insulating film so that the vias are gap-filled with the tungsten; forming tungsten plugs by performing a tungsten chemical mechanical polishing process to remove excess tungsten deposited over the upper portion of the lower insulating film; removing the tungsten remaining over the upper portion of the lower insulating film by performing a tungsten etchback process; depositing an upper insulating film over the upper portion of the lower insulating film; exposing upper portions of the tungsten plugs by forming trenches on the upper insulating film; depositing copper over the entire surface of the upper insulating film so that the trenches are gap-filled with the copper; and planarizing the copper over the upper portion of the trenches.

Abstract: A digital synchronous circuit includes a clock generator for generating a reference clock signal, a plurality of delays for delaying the reference clock signal by predetermined different times, a transition varying buffer for controlling input transitions of the clock signals received from the plurality of the delays, a transition controller for controlling operation of the transition varying buffer, and a plurality of registers driven by the clock signals from the plurality of delays.