Patents Represented by Attorney, Agent or Law Firm Shirley L. Church, Esq.
  • Patent number: 7879409
    Abstract: We have a method of improving the deposition rate uniformity of the chemical vapor deposition (CVD) of films when a number of substrates are processed in series, sequentially in a deposition chamber. The method includes the plasma pre-heating of at least one processing volume structure within the processing volume which surrounds the substrate when the substrate is present in the deposition chamber. We also have a device-controlled method which adjusts the deposition time for a few substrates at the beginning of the processing of a number of substrates in series, sequentially in a deposition chamber, so that the deposited film thickness remains essentially constant during processing of the series of substrates. A combination of these methods into a single method provides the best overall results in terms of controlling average film thickness from substrate to substrate.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: February 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Gaku Furuta, Tae Kyung Won, John M. White
  • Patent number: 7864503
    Abstract: A capacitive type touch panel includes: a transparent substrate; an array of first conductors formed on a surface of the transparent substrate; an array of second conductors formed on the surface of the transparent substrate; a plurality of conductive first bridging lines, each of which interconnects two adjacent ones of the first conductors; a plurality of conductive second bridging lines, each of which interconnects two adjacent ones of the second conductors and each of which intersects insulatively a respective one of the first bridging lines; and a plurality of spaced apart insulators, each of which is disposed at an intersection of a respective one of the first bridging lines and a respective one of the second bridging lines to separate the respective first and second bridging lines.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: January 4, 2011
    Assignee: Sense Pad Tech Co., Ltd
    Inventor: Yu-Huei Chang
  • Patent number: 7795138
    Abstract: We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 14, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 7737040
    Abstract: An anti-reflective hard mask layer left on a radiation-blocking layer during fabrication of a reticle provides functionality when the reticle is used in a semiconductor device manufacturing process.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: June 15, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Dennis Bencher, Melvin Warren Montgomery, Alexander Buxbaum, Yung-Hee Yvette Lee, Jian Ding, Gilad Almogy, Wendy H. Yeh
  • Patent number: 7696117
    Abstract: A ceramic article which is resistant to erosion by halogen-containing plasmas used in semiconductor processing. The ceramic article includes ceramic which is multi-phased, typically including two phase to three phases. The ceramic is formed from yttrium oxide at a molar concentration ranging from about 50 mole % to about 75 mole %; zirconium oxide at a molar concentration ranging from about 10 mole % to about 30 mole %; and at least one other component, selected from the group consisting of aluminum oxide, hafnium oxide, scandium oxide, neodymium oxide, niobium oxide, samarium oxide, ytterbium oxide, erbium oxide, cerium oxide, and combinations thereof, at a molar concentration ranging from about 10 mole % to about 30 mole %.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 13, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jennifer Y. Sun, Ren-Guan Duan, Jie Yuan, Li Xu, Kenneth S. Collins
  • Patent number: 7687909
    Abstract: A metal/metal nitride barrier layer for semiconductor device applications. The barrier layer is particularly useful in contact vias where high conductivity of the via is important, and a lower resistivity barrier layer provides improved overall via conductivity.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 30, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Peijun Ding, Zheng Xu, Hong Zhang, Xianmin Tang, Praburam Gopalraja, Suraj Rengarajan, John C. Forster, Jianming Fu, Tony Chiang, Gongda Yao, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara
  • Patent number: 7589016
    Abstract: A method of applying a sculptured copper seed layer on a semiconductor feature surface using ion deposition sputtering. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: September 15, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 7459003
    Abstract: A space-conserving integrated fluid delivery system which is particularly useful for gas distribution in semiconductor processing equipment. The invention pertains to a diffusion bonded integrated fluid flow network architecture, which includes, in addition to a layered substrate containing fluid flow channels, an in-line filter and may include various fluid handling and monitoring components. The integrated fluid delivery system that is formed from a layered substrate is diffusion bonded, and the various fluid handling and monitoring components may be partially integrated or fully integrated into the substrate, depending on design and material requirements.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: December 2, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Mark Crockett, John W. Lane, Micahel DeChellis, Chris Melcer, Erica Porras, Aneesh Khullar, Balarabe N. Mohammed
  • Patent number: 7381639
    Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 3, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 7262116
    Abstract: A method of preparing a clean substrate surface for blanket or selective epitaxial deposition of silicon-containing and/or germanium-containing films. In addition, a method of growing the silicon-containing and/or germanium-containing films, where both the substrate cleaning method and the film growth method are carried out at a temperature below 750° C., and typically at a temperature from about 700° C. to about 500° C. The cleaning method and the film growth method employ the use of radiation having a wavelength ranging from about 310 nm to about 120 nm in the processing volume in which the silicon-containing film is grown. Use of this radiation in combination with particular partial pressure ranges for the reactive cleaning or film-forming component species enable the substrate cleaning and epitaxial film growth at temperatures below those previously known in the industry.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: August 28, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, David Carlson, Manish Hemkar, Satheesh Kuppurao, Randhir Thakur
  • Patent number: 6758947
    Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: July 6, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 6271592
    Abstract: The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques with specific process conditions results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer of an oxygen-stuffed barrier metal (MOx), an oxygen-stuffed nitride of a barrier metal (MNOx), or a combination thereof; (c) a third layer of a nitride of a barrier metal (MNx), deposited by IMP sputter deposition of the barrier metal in the presence of nitrogen; and (d) a fourth, wetting layer of a barrier metal, deposited by traditional sputter deposition.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 7, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Edwin Kim, Michael Nam, Chris Cha, Gongda Yao, Sophia Lee, Fernand Dorleans, Gene Y. Kohara, Jianming Fu