Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: An interactive study aid provides student- or other source-selected (208) questions for studying. Preferably in conjunction with machine-implemented or other information processing, the interactive study aid of the present invention provides a student with the ability to acquire, present/study, and collaborate upon study material (202) information. Acquisition of study material (202) information may be made through soft-text resources such as digital books or online resources. A pen scanner may be used to access hard copy information making pertinent portions available to the interactive study aid. Study material information may also be entered by hand. Upon entering the study material, the student can indicate the likelihood of its appearing on a test or the importance of the information to the student.

Abstract: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands.

Abstract: A write pole tip for a magnetic head has a trailing edge that is closer than a leading edge to a perpendicular recording medium, so that the write signal strength of the trailing edge is greater than that of the leading edge. Such an angled pole tip can write a sharp magnetic pattern with the trailing edge, reducing erroneous writing. A layer of physically hard material such as diamond-like carbon (DLC) may adjoin the trailing edge, the physically hard material layer protruding slightly after polishing of the media-facing surface due to its resistance to lapping. This can form an acute corner of the write pole tip adjacent to the physically hard material layer. The trailing edge may be longer than the leading edge, and the write pole tip may have a trapezoidal shape.

Abstract: A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The TONID also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the TONID to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the TONID as a communication control block (CCB) that can be passed back to the host for message processing by the host. The TONID contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: An artificial candle has a delicate glowing shroud or sock that can flutter like a candle flame, and the sock may surround a “wick” that can be seen through the sock to glow. Such a diaphanous sock can be actuated by a fan, air pump, solenoid or conductor, which can be provided adjacent to the sock or removed from the sock, for example in a central body of a chandelier. Light can emanate from the wick from a light emitting diode (LED), and the sock can include fluorescent material that absorbs and reradiates some of the light from the wick. The wick and the sock can be coupled to a shaft that simulates a wax candle body. A standard threaded fitting can be provided so that the artificial candle can thread into a socket to replace a light bulb.

Abstract: A retaining wall or steeply faced slope is disclosed having a naturally green façade. The wall or slope is made of blocks of compacted earth, each having a face reinforced with wire mesh and covered with vegetation such as native grasses. The blocks may be formed onsite, saving transportation costs and other waste, using native soils. The mesh may extend beyond other faces of each block to provide handles and geogrid anchoring. A press is disclosed to form the blocks by compacting soil mixed with cement, the press including hydraulic rams or screw jacks that create immense pressures and having wedge shaped sides that relieve lateral confining pressure when the block is extracted. The wall may be expected to last indefinitely, despite the vegetation growing on it.

Abstract: A method and apparatus for providing specifically targeted advertisements and preventing various forms of advertising fraud in electronic books.

Abstract: A host CPU runs a network protocol processing stack that provides instructions not only to process network messages but also to allocate processing of certain network messages to a specialized network communication device, offloading some of the most time consuming protocol processing from the host CPU to the network communication device. By allocating common and time consuming network processes to the device, while retaining the ability to handle less time intensive and more varied processing on the host stack, the network communication device can be relatively simple and cost effective. The host CPU, operating according to instructions from the stack, and the network communication device together determine whether and to what extent a given message is processed by the host CPU or by the network communication device.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: The present invention relates to stable, palatable, freeze-dried, fruit-based compositions. Specifically, the inventions relates to compositions of Açai fruit and Jucara fruit with high antioxidant capability and cyclooxygenase-inhibitory activity, and their uses. The invention further provides for methods of making stable, palatable, freeze-dried, fruit-based compositions from Açai fruit and Jucara fruit.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: A host computer running a TCP connection transfers the connection to a TCP offload network interface device (NID) which performs certain network processes, thereby reducing the load on the host CPU. The NID later transfers the connection back to the host. The host and the NID maintain separate timestamp clocks which provide timestamp values for connections using the TCP Timestamp option. Synchronization of the host and NID timestamp clocks can be realized by transfer of a clock value. The NID or host receives the transferred TCP connection and the transferred clock value, and decides whether to update its own clock to equal the transferred clock value, the decision being guided by the requirement to never allow the timestamp clock to run backward. Acceleration of the timestamp clocks is prevented so that RTT measurements are accurate. Synchronization of the host and NID timestamp clocks improves performance and reduces erroneous connection drops.

Abstract: A network interface device has a fast-path ACK generating and transmitting mechanism. ACKs are generated using a finite state machine (FSM). The FSM retrieves a template header and fills in TCP and IP fields in the template. The FSM is not a stack, but rather fills in the TCP and IP fields without performing transport layer processing and network layer processing sequentially as separate tasks. The filled-in template is placed into a buffer and a pointer to the buffer is pushed onto a high-priority transmit queue. Pointers for ordinary data packets are pushed onto a low-priority transmit queue. A transmit sequencer outputs a packet by popping a transmit queue, obtaining a pointer, and causing information pointed to by the pointer to be output from the network interface device as a packet. The sequencer pops the high-priority queue in preference to the low-priority queue, thereby accelerating ACK generation and transmission.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.