Abstract: A memory device is disclosed that operates internally substantially independent of the timing of signals from its associated computer. That is, the timing controls for multiplexing the row and column address into the memory chips as well as the enabling signal for writing information into the chips are controlled by different delay lines so that the memory always operates at its optimal operational speed. In addition, the input and output latches are arranged to receive or output information to or from the computer at a time that is optimal for the computer or other information requester.

Abstract: A circuit is described for discriminating relatively wide, high level signal pulses from relatively narrow and/or low level noise pulses. The input pulses are first passed through a first Schmitt trigger to eliminate low level noise pulses. The output of the first Schmitt trigger is connected to a signal input of a "D" latch and to one input of an exclusive NOR gate. The exclusive NOR gate compares the input pulses from the output of the first Schmitt trigger with an output of the latch through a second Schmitt trigger. An R-C integrating network connected between the exclusive NOR gate and the second Schmitt trigger produces a rising input signal to the second Schmitt trigger that reaches the threshold level of the Schmitt trigger only for input signal pulses that exceed a given pulse width.