Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: A computer system is upgraded while the computer system is functioning. The computer system has a first boot device with a first operating system and a second device. The method includes: preparing the second device within the computer system as a bootable device while the computer system is functioning under control of the first operating system; preparing the second device within the computer system to receive a second operating system while the computer system is functioning under control of the first operating system; loading the second operating system onto the second device while the computer system is functioning under control of the first operating system; and, rebooting the computer system such that the computer system is under control of the second operating system on the second device.

Abstract: A plasma resistant lightpipe is used in a pyrometric temperature measurement system to measure the temperature of a substrate in a reaction chamber. The plasma resistant lightpipe includes two lightpipe elements. The first lightpipe element, which may be a sapphire rod or aluminum nitride rod, is positioned within a backside gas delivery path to the chamber. The first lightpipe element is resistant to etching caused by reactive plasmas or gases used within the chamber, such as fluorine. The second lightpipe, which is a quartz rod, is positioned beneath the first lightpipe element such that the two lightpipe elements are optically coupled. The first lightpipe element may be directly mounted in the base plate or electrostatic chuck of the pedestal assembly or directly mounted in a plug, which is then positioned within the base plate or electrostatic chuck.

Abstract: An encrypted part of the encrypted program loaded in an memory device is received by a one-chip microcomputer and decrypted according to a decrypting program which is stored in advance in an ROM and which cannot be read out to an external bus. The decrypted program is stored in an cache memory, and a cache function inhibition flag is set in a control register in accordance with a storage area of the decrypted program in the cache memory. Therefore, the decrypted program is inhibited from being read out to the external bus. The decrypted program is combined with the non-encrypted part of the program stored in the memory device, and the combined program is executed by a CPU. The encrypted program is prevented from being illegally copied.

Abstract: An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.

Abstract: A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected elements of a reference cell are electrically erased and reprogrammed for accurately tuning the sensing of multiple data states in a memory cell. For example, 64 or more data states may be tuned so that a single megabyte of memory is allocated to store six megabytes of information.

Abstract: A magnetic recording member with a thin metallic antifriction protection overcoat formed over a magnetic layer. The overcoat is soft ductile and low stress and includes a metal selected from the group consisting of palladium, platinum, silver, gold, cadmium, indium, tin and lead or an alloy of one or more of these metals, and may include less than 20 percent by weight of antimony, bismuth, thallium or copper to improve wear resistance or impede corrosion. In one preferred embodiment the antifriction overcoat is an alloy of silver, lead and antimony formed with N layers where 10.ltoreq.N.ltoreq.40. The even layers are richer in a selected metal of the alloy than the odd layers in order to produce adjacent layers with different lattice or microstructural and associated mechanical properties so that there tends to be parallel shear between adjacent layers under sharing stress of head impact or friction.