Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.

Abstract: A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.

Abstract: A family of related programmable logic devices is provided. The family includes a first programmable logic device having n number of logic modules. The first programmable logic device is incorporated into a first package, with the n number of logic modules bonded out to the first package. A second programmable logic device has a number of logic modules greater than n. The second programmable logic device is incorporated into a second package of substantially the same size as the first package and having an identical pin assignment, with only n number of the logic modules of the second programmable logic device bonded out to the second package.

Abstract: In one aspect, a network system includes a user interface which allows a user to interact with the network system. An agent server is coupled to the user interface. The agent server manages the operation of the network system. Furthermore, the agent server in conjunction with the user interface is operable to create or modify an agent in response to interaction by the user. In another aspect, a network system includes an agent server which manages the operation of the network system. An agent is operable to utilize a service within the network system. A service wrapper, associated with the service, cooperates with the agent server to mediate interaction between the service and the agent.

Abstract: A programmable logic device having an internal tristate bus is provided. The internal tristate bus may be driven by a plurality of driving elements. Such a tristate bus, and the circuitry for supporting it, can be implemented on less surface area than the multitude of unidirectional buses, and supporting circuitry, which would otherwise be required for the same plurality of driving elements. Accordingly, the amount of surface area that is required to move information within a programmable logic device is reduced. Furthermore, in one embodiment, a arbitration logic circuit is provided for each driving element. These arbitration logic circuits cooperate to prevent the different elements from simultaneously driving the internal tristate bus. Accordingly, the integrity of the information on such bus is maintained.

Abstract: A reciprocating friction-type mirror finishing machine which has a simple construction and performs easily adjustable feeding mode under micrometer scale is disclosed. This machine includes a driving device for generating a driving force in response to a swing motion thereof, and a friction device connected with the driving device for performing alternately clockwise and counterclockwise rotation relative to a work stand in contact therewith to generate a linearly reciprocating frictional force in response to the driving force. The frictional force allows a work piece held by the work stand to be fed in a linearly reciprocating motion to be ground.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ("FPGA"). The memory device can provide the configuration data on a serial output lead or a parallel data bus.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.