Abstract: A device interface module provides multiple concurrently operating data transfer channels between multiple groups of peripheral devices and ad multiported buffer memory which communicates via an interface bus to other external modules of a computer system.

Abstract: A variable buoyancy buoy includes a shell and expansion apparatus. The two are combined in a manner to provide a watertight structure with an internal region wherein a constant pressure is maintained that is substantially equal to the pressure at a predetermined depth below the water surface. At depths above the predetermined depth the internal pressure is greater than the external water pressure. This differential pressure causes the buoy to expand, thereby increasing its buoyancy.

Abstract: Clutter reduction is accomplished by dividing the sampling times of received radar signals into blocks containing a plurality of sampling times. The average clutter value in each block is estimated by averaging the signal returns for the sampling times in the block. Block average clutter values are time positioned at a selected sampling time position in a block and a smooth function with continuous first and second derivatives is passed through the average clutter value points. In a preferred embodiment the smooth function is a cubic spline comprising third order polynomial segments between average clutter value points. Clutter values at the sampling points are extracted from the smooth function and respectively subtracted from the received radar signals. A clutter sensor examines the resulting radar signals for clutter distortion and eliminates radar signals that are not substantially clutter free.

Abstract: A method and apparatus for resolving Doppler frequency shift ambiguities in pulse Doppler radar systems provides a radiated signal that is modulated with a periodic waveform having a plurality of pulses within a period, the interpulse intervals between pulses in the period being unequal. Radar target returns are autocorrelated for a plurality of lags, which may include the interpulse intervals and linear combinations thereof. The calculated arguments .theta..sub.Ci of the autocorrelation function are unwrapped by adding 2k.sub..pi., k=0, .+-.1, .+-.2, . . . , to the phase .theta..sub.C1 obtained for the shortest lag T.sub.1 and determining an integer m.sub.k2 from .vertline.(.theta..sub.C2 +2m.sub.k2 .pi.)-(T.sub.2 /T.sub.1).theta..sub.C1 .vertline. <.pi. and then setting .theta..sub.2 =.theta..sub.C2 +2m.sub.k2 .pi.. Phase angles .theta..sub.3, .theta..sub.4, . . . , .theta..sub.m are unwrapped in a similar manner, the integer m.sub.ki being determined from .vertline.(.theta..sub.Ci +2m.sub.ki .pi.)-(T.

Abstract: An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical base address and page index of the targeted word resides in an associated set of CAMs and RAMs. If the targeted word's logical base address and page index is not in the set of associated CAMs and RAMs, this information can be acquired at the most optimum rate for enabling data access. This rate may require several clock cycles.

Abstract: An electro-mechanical assembly includes a high power IC package and a low power IC package which are mounted with a space between them on a single substrate. Both of these IC packages have flat top surfaces which dissipate heat; and due to various manufacturing tolerances, those surfaces are non-coplanar with respect to each other. To cool these two IC packages, a single heat sink is provided which has a thin flat core that overlies both of the IC packages as well as the space between them, and cooling fins extend from the top of the core.

Abstract: A system for updating logical address data in pointers used by a processor in a computer system using paged memory. An Actual Segment Descriptor Associative Memory System (ASDAM) provides a dual cache memory for searching page table logical addresses and page index values which can, if available, provide a logical address, via a logical address RAM, to update a pointer in one machine cycle, with a new logical address. If the required data is not available in the dual cache memory, then other circuitry is operative to translate logical addresses into physical addresses permitting rapid access to main memory in order to supply the dual cache memory and logical address RAM with the required data.

Abstract: In a digital data transfer system whereby a plurality of driver units are all connected to and share the same common system bus, there is provided control gating logic which will prevent the enablement of a subsequent driver for a fixed delay time until it is certain that the previous driver has been shut down. Due to switching time variations in driving units, a fixed delay time is set to function in a first driver that is beginning its data transmission to be sure that another driver which was previously transmitting data has been completely turned-off before the first driver gains access to the commonly shared bus. This ensures that no two drivers can simultaneously be driving data onto the system bus at the same time which would obviate the integrity of data transmitted.

Abstract: Apparatus and method are provided whereby a single rocket or other projectile can be used to deploy a flexible array such as a net. There is provided to the rocket, via a sleeve and an attached flexible nose cone cap, a pair of pivoted, telescoping arms. The rocket is placed in a launch tube that has guides for the rocket, accommodates the swing arms, and has guides for the tow cables for the net. When the rocket is launched from the launch tube, the arms are swung apart on their single pivot such as with one or more loaded springs. After the arms have been swung out, they are held in place such as by a clam shell catch spring. While or after the spring-loaded arms are spread into place, the telescoped arms are extended such as by triggering a gas generator. Tow cables, one attached to each extreme end of an arm, spread out the net while the rocket is pulling it. Stabilization cables are provided that provide a central point of tow contact and better distribute some loads.

Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. Process temperatures are limited such that all dopant atoms are interstitial in the semiconductor crystals and not substitutional.

Abstract: An instrument for indirectly measuring the attitude of a moving aircraft includes three accelerometers, a GPS radio receiver, an electronic estimating module, and an electronic output module. The three accelerometers indicate three accelerations of the aircraft respectively along three aircraft body axes. The GPS radio receiver receives from GPS satellites the position and velocity of the aircraft along an earth fixed axis. The electronic estimating module estimates a vector such that a series of aircraft position changes along the three body axes that are caused by the measured accelerations, times the vector, approximately matches a corresponding series of position changes along the earth fixed axis as given by the receiver. The electronic output module generates a visual display of the roll, pitch, or heading of the aircraft by performing trigonometric functions on the vector.

Abstract: A bus interface transfer system enables communication to/from dual busses to multiple resource units which include a central processor module and a translation logic unit which permits data transfer between systems having different protocols and different clock rates.

Abstract: This is a commercial capable heavy lifter capable of rotating or levering large objects up and down by remote control. When used to so raise and lower targets on a firing range, the target can be dropped automatically when the target receives one or more hits.

Abstract: A mass storage/retrieval module for controlling the storage and retrieval operations of massive amounts of data in peripheral devices such as tape, disk, optical, etc. provides for a buffer memory system in each of the interface control modules which permit simultaneous and concurrent writing to buffer storage and reading out of buffer storage through multiple ports for high rates of data transfer operations. Redundancy and high reliability is provided in that each module of the system has dual busses and live replacement units such that, upon failure, an alternate unit can carry the circuitry requirements until the failing unit has been replaced.

Abstract: A spectral moment estimator includes a first processor which processes signals representative of the magnitudes of complex autocorrelation functions of a signal at a plurality lags and provides Doppler spectral width representative signals and the autocorrelation function at zero lag independent of noise. A second processor, processes the complex autocorrelation representative signals, the complex autocorrelation functions phase angles representative signals, and the Doppler spectral width representative signals to provide the mean Doppler frequency of the the signal. The autocorrelation function phase angles are disambiguated and the unambiguous phase angles are least mean square error fitted to a third order odd polynomial, the linear term of which is the mean Doppler frequency of the signal.

Abstract: An element responsive to acoustic particle acceleration for sensing acoustic signals in a region of low acoustic pressure is disclosed. The element may be isolated from acoustic noise when positioned adjacent an acoustic noise generating high acoustic impedance structure by a baffle which provides isolation from radiated and evanescent acoustic signals and structure vibration.

Abstract: A mine countermeasure device includes a passthrough mechanism and a mine neutralization package. The passthrough mechanism includes a first wheel with a raised rim and at least one radially oriented slot or notch, a clevis member rotatably engaging the axle of the first wheel, and a bail member slidably engaging the underside of the rim. A smaller wheel is pivotably connected at its axle to an angled member extending from the neutralization package. The neutralization package also includes a collapsed float, a gas generator to inflate the float, explosives to neutralize a mine, and an electric detonator for the explosives. The passthrough device is towed underwater by a sweep wire connected to the clevis member and to the bail member. When the sweep wire encounters a mine mooring, the sweep wire is pulled along the mooring until the mooring enters a slot of the first wheel.

Abstract: An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.

Abstract: An apparatus and method for handling the connection/disconnection transition period of a printed circuit board to an actively empowered backplane which eliminates damaging surge currents and glitches by the use of temporarily functioning field effect transistor circuits which gradiently handle the current loads during the transition period. A set of specifically sized and predetermined lengths of connecting pins on the backplane insures that a programmed sequence of power connection and/or disconnection will occur which permits a group of field effect transistors to gradiently carry the changing current loads that occur during the insertion of the printed circuit board into the backplane. Likewise, during extraction of the printed circuit board from the backplane, the group of FETs (Field Effect Transistors) will carry and buffer the changing current loads from de-stabilizing the power supply source unit.

Abstract: A power distribution and control system for computer modules having minimal parts and volume for attachment to a computer cabinet frame which acts as a heatsink. The AC source is split into multiple (M) distribution channels, each of which is monitored by a control unit which operates a solid state relay which permits and/or cuts off line current in that channel. The control units are concatenated so that each current distribution channel operates through 3 through 5 AC cycles before the next succeeding distribution channel is activated. However, each control unit in the system can be individually programmed via external signals.