Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract: A new method to form split gate flash memory cells in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. Pairs of floating gates are formed overlying the substrate. Common source plugs are formed overlying the substrate and filling spaces between the floating gate pairs. An oxide layer is formed overlying the substrate, the floating gates, and the common source plugs. A conductor layer is deposited overlying the oxide layer. First dielectric spacers are formed on vertical surfaces of the conductor layer. The conductor layer is etched through where not covered by the first dielectric spacers to thereby form word line gates adjacent to the floating gates. Second dielectric spacers are formed on vertical surfaces of the word line gates and the first dielectric spacers to complete the split gate flash memory cells.

Abstract: A circuit and method are given, to realize a high voltage output driver within a closed regulator loop with slew rate control, insensitive against supply voltage variations. The high-voltage front-end, essentially a slope detector, is implemented as a combination of a voltage-current with a current-voltage transformer circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only two discrete or integrated extended drain MOS components at low cost.

Abstract: A new method is provided for forming salicided surfaces to a FET device. Gate electrodes are formed including Ti/TiN salicided contact surface regions thereto. A thin layer of silicon oxide and a thick layer of photoresist are deposited. The layer of photoresist is polished, stopping on a top layer of BN of the gate electrode. The exposed layer of BN is removed. A thick layer of Ti/TiN is next deposited and annealed, forming TiSix after which unreacted Ti/TiN is removed. A high temperature anneal is applied to reduce the sheet resistance of the layer of TiSix. As an alternate approach to the above cited sequence the layer of photoresist can be replaced with a layer of boro-phosphate-silicate-glass (BPSG), the layer of BN can be replaced with a layer of silicon nitride.

Abstract: A highly stable single chip resonator controlled oscillator with automatic amplitude control and biasing is designed for manufacture with monolithic integrated circuit technologies. Analog and digital output buffers with elaborate control for power saving purposes and sophisticated start-up and power-up circuits ensure, that a crystal controlled oscillation is safely induced at start-up and that the amplitude of oscillation is continuously controlled during operation to reach low phase noise and reduce power consumption of the circuit.

Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.

Abstract: A circuit and method are given, to realize a high-voltage control and driver interface as integrated circuit, especially for use in connection with four external components, inductor L and capacitor C as well as low-side and high-side switching transistors as found e.g. in half-bridges. The circuit is essentially self supplied by means of an Intrinsically floating auxiliary supply power generation and regulation scheme. The circuit is apt to supporting high main supply voltages up to 1000V. The circuit of the invention is realized without the need for any internal high-voltage integrated semiconductor devices. Exploiting the advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete external components, which is favorably lowering the cost of production.

Abstract: A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is disposed over the active regions. Finger-like floating gates are equally spaced along the active regions. The finger-like floating gates are comprised of a conductive base section that is disposed over the gate dielectric layer and three conductive finger sections that are in intimate electrical contact with the base section. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region. Word lines, which are composed of a third conductive layer, are parallel lines disposed over the interlevel dielectric layer and serve as control gates.

Abstract: In bottom spin valves of the lead overlay type the longitudinal bias field that stabilizes the device tends to fall off well before the gap is reached. This problem has been overcome by providing a manufacturing process that includes inserting an additional antiferromagnetic layer between the hard bias plugs and the overlaid leads. This additional antiferromagnetic layer and the lead layer are etched in the same operation to define the read gap, eliminating the possibility of misalignment between them. The extra antiferromagnetic layer is also longitudinally biased so there is no falloff in bias strength before the edge of the gap is reached. A process for manufacturing the device is also described.

Abstract: An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell of each row is connected to a word line and a source select line, and each memory cell of each column connected to a first bit line and a second bit line. Each memory cell is composed of a first transistor and second transistor. The first and second transistors have control gate connected to the word line receive a word line voltage, a source connected the source select line to receive a source line voltage, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The first transistor has a drain connected the first bit line to receive a first bit line voltage and the second transistor a drain connected to the second bit line to receive a second bit line voltage.

Abstract: A magnetic read head with reduced side reading characteristics is described. This design combines use of a current channeling layer (CCL) with stabilizing longitudinal bias layers whose magnetization direction is canted relative to that of the free layer easy axis and that of the pinned layer (of the GMR). This provides several advantages: First, the canting of the free layer at the side region results in a reduction of side reading by reducing magnetic sensitivity in that region. Second, the CCL leads to a narrow current flow profile at the side region, therefore producing a narrow track width definition. A process for making this device is described. Said process allows some of the requirements for interface cleaning associated with prior art processes to be relaxed.

Abstract: A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.

Abstract: A method for forming top and bottom spin valve sensors and the sensors so formed, the sensors having a strongly coupled SyAP pinned layer and an ultra-thin antiferromagnetic pinning layer. The two strongly coupled ferromagnetic layers comprising the SyAP pinned layer in the top valve configuration are separated by a Ru spacer layer approximately 3 angstroms thick, while the two layers in the bottom spin valve configuration are separated by a Rh spacer layer approximately 5 angstroms thick. This allows the use of an ultra thin MnPt antiferromagnetic pinning layer of thickness between approximately 80 and approximately 150 angstroms. The sensor structure produced thereby is suitable for high density applications.

Abstract: An apparatus for solving an edge exclusion problem when polishing a semiconductor wafer includes a rotatable polishing platen with a polishing pad attached to its upper surface. A polishing slurry is deposited on the upper surface of the polishing pad during polishing. Mounted above the polishing pad is a rotatable polishing head for holding a substrate. A non-rotary actuator assembly is coaxially oriented about the outer edge of the polishing head. A ditched ring is removably attached to the bottom surface of the actuator assembly. A multiplicity of conduit grooves are formed in the bottom section of the ditched ring that allows the polishing slurry to travel unimpeded beneath the rotating wafer. A reduced wall thickness at the bottom of the ditched ring is configured to displace wrinkles from the outer edge of the wafer to the outer periphery of the ditched ring. This solves the edge exclusion problem while permitting polishing slurry to pass under the wafer.

Abstract: This invention describes a novel production method of manufacturing metal/ceramic articles with complex internal undercut features using powder injection molding processes The shape of the undercut/hollow feature is initially molded using a disposable material such as a degradable polymer. The PIM feedstock is then molded onto this to form the required shape geometry, in effect encapsulating the polymeric feature in the PIM feedstock. The resulting two-material part is then sent for processing which removes the polymer through solvent or thermal process. After the polymer and the binder have been removed, the part now comprises a powder skeleton that contains the internal undercut feature within itself. After sintering the result is a metal/ceramic part having an internal undercut feature. The technical advantage of the present invention is that it does not require complex toolings or costly secondary operations while retaining the flexibility to design any internal undercut features of complex geometry.

Abstract: Currently it takes up to 10 mA current in the programming line to switch a cell in an MRAM. This current is high enough to cause electro-migration problems over the life of an array so there is a need for a more efficient way to generate the programming field. The present invention solves this problem by (1) passing the programming current inside the cell, i.e, through the pinned layer, and (2) surrounding each program line with a sheath of high permeability material which covers the wire except for a gap located directly above or below the memory element. This high permeability layer may be a conductor or an insulator, the latter case allowing it to make direct contact with the memory element.

Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.

Abstract: A new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment, a hardmask layer over a substrate and a layer of ARC over the hardmask layer are successively patterned. The patterned layer of ARC is removed, the remaining patterned hardmask layer is used as a mask for etching the substrate. Under the second embodiment, a first hardmask layer over a substrate, a second hardmask layer over the first hardmask layer and a layer of ARC over the second hardmask layer are successively patterned. The patterned layer of ARC and the second hardmask layer are removed, the remaining first patterned hardmask layer is used as a mask for etching the substrate.

Abstract: A new optical lithographic exposure apparatus is described. The apparatus may comprise, for example, a lithographic stepper or scanner. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through one of the first mask and the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A step and scan method using the mask stage is provided. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus. The first mask and the second mask are aligned. The first mask is scanned. The wafer is then stepped. The second mask is scanned.

Abstract: A method for forming a plated magnetic thin film of high saturation magnetization and low coercivity having the general form Co100−a−bFeaMb, where M can be Mo, Cr, W, Ni or Rh, which is suitable for use in magnetic recording heads that write on narrow trackwidth, high coercivity media. The plating method includes four current application processes: direct current, pulsed current, pulse reversed current and conditioned pulse reversed current.