Abstract: A method is provided for generating a pulse signal with modulable-width pulses. A set-point signal is generated and compared with a control signal so as to produce the pulse signal. When the control signal is a two-state logical signal, a first reference voltage is taken as the set-point signal. When the control signal is a continuous analog voltage, the set-point signal is varied between the first reference voltage and a predetermined second reference voltage, which is higher than the first reference voltage. Also provided is a device for generating a pulse signal with modulable-width pulses. The device includes a set-point signal generator, a control signal generator, and a comparator that outputs the pulse signal. The set-point signal generator includes a first voltage source for generating a first reference voltage, and a second voltage source for generating a second reference voltage, which is higher than the first reference voltage.

Abstract: A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Abstract: A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line.

Abstract: A voltage regulation device is provided for receiving a voltage at an input node and supplying a regulated voltage to electronic circuitry at an output node. The device includes a switching circuit that is coupled between the input node and the output node, and a control circuit that is coupled to the switching circuit. When the voltage level at the output node is below a threshold voltage, the control circuit controls the switching circuit so as to substantially short-circuit the input node and the output node. On the other hand, when the voltage level at the output node is not below the threshold voltage, the control circuit controls the switching circuit so as to substantially isolate the input node from the output node. In a preferred embodiment, the switching circuit includes an NMOS transistor, and the control circuit includes a differential amplifier that supplies a control signal to the gate of the NMOS transistor. A smart card containing a voltage regulation device is also provided.

Abstract: An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).

Abstract: An activation signal generating circuit includes a combinational logic circuit and a switch. The combinational logic circuit receives a normal mode control signal and a test mode control signal, and the switch receives a periodic clock signal. The switch is controlled by the output of the combinational logic circuit such that an activation signal is generated from the periodic clock signal. In one preferred embodiment, the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, and a potential setting circuit imposes a specified potential at the output of the switch when the switch is open. A method of generating an activation signal is also disclosed.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: A carrier of semiconductor wafer transportation. The carrier comprising: a base; two or more walls mounted to the base, with a plurality of grooves for receiving wafers by lateral insertion thereinto through a mouth, the mouth defined by an upper wall and a substantially horizontal lower wall, wherein the groove comprises a closed end defined by a back wall joined to the upper wall and the lower wall so that the groove narrows from the mouth towards the closed end, the upper wall being slanted upward towards the mouth and the back wall being slanted towards the mouth in the region close to the horizontal wall.

Abstract: A circuit is provided for supplying a load from an AC voltage supply. The circuit includes a control circuit and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on a relatively low DC voltage. The bidirectional switch is connected to a first terminal of the AC voltage supply, and the DC voltage is referenced to the first terminal of the AC voltage supply. Additionally, an apparatus connected to an AC voltage supply and a relatively low DC voltage is provided. The apparatus includes a control circuit, a load to be supplied by the AC voltage supply, and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on the DC voltage.

Abstract: A method of providing information from a database to a user's system. According to the method, database query results are stored in a source code files and the source code files are compiled to provide compiled files. When information from the database is requested, at least one of the compiled files is downloaded to the user's system. In one preferred information providing method, the source code files are in the form of Java source code files and the compiled files are in the form of Java class files.18. Additionally, a method is provided for retrieving information from a database on a remote system for use on a user's system. A request for database information is transmitted over a network from the user's system to the remote system, and in response at least one compiled database result file is downloaded from the remote system. Each of the compiled database result files is used to store database query results in executable or bytecode form.

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.

Abstract: A voltage phase generator that generates a normal voltage phase, a negated normal voltage phase, a boosted voltage phase, and a negated boosted voltage phase. The voltage phase generator includes a first driver circuit that supplies the normal voltage phase to a first output node, and a second driver circuit that supplies the negated normal voltage phase to a second output node. The first and second driver circuits are driven by additional voltage phases that have a boosted voltage. In one preferred embodiment, each of the driver circuits includes a pull-up connected between a supply voltage and one of the output nodes, and a pull-down connected between ground and the one output node. Additionally, the present invention provides a voltage boosting circuit that includes a booster circuit and a voltage phase generator.

Abstract: A method for scaling an input bitmap by a non-integer factor with improved image quality comprises the steps of: selecting a pel in the input bitmap; selecting a neighborhood surrounding the selected pel; searching a set of image feature patterns to find an image feature pattern that matches the selected neighborhood; and writing a blocks of bits to an intermediate bitmap based on the match. The appropriate block of bits is obtained by subsampling an image enhancing tile which corresponds to the matched image feature pattern. The process of matching neighborhoods and writing a subsampled image enhancing tile (i.e., block of bits) to the intermediate bitmap is repeated for each pel in the input bitmap. When the image enhancing tiles are subsampled to the proper size and shape and placed in the proper locations in the intermediate bitmap, the jagged “stair-step” look of curved and diagonal image features in the input image is smoothed, resulting in improved quality.

Abstract: A device is provided for neutralizing an electronic circuit whose rate is set by a clock signal in the event of an anomaly in the clock signal. The device includes an inhibition circuit for selectively inhibiting operation of the electronic circuit, and an anomaly detector for activating the inhibition circuit to inhibit operation of the electronic circuit as soon as an anomaly is detected in the clock signal. In one preferred embodiment, the anomaly detector includes two monostable circuits and a logic circuit. The first monostable circuit receives the clock signal and outputs a first pulse at each trailing edge of the clock signal, and the second monostable circuit receives the clock signal and outputs a second pulse at each leading edge of the clock signal. The logic circuit receives the first and second pulses and outputs an activation signal to the inhibition circuit whenever the clock signal shows an anomaly.

Abstract: A method for scaling an input bitmap by a non-integer factor with improved image quality comprises the steps of: selecting a pel in the input bitmap; selecting a neighborhood surrounding the selected pel; searching a set of image feature patterns to find an image feature pattern that matches the selected neighborhood; and writing a blocks of bits to an anamorphically scaled intermediate bitmap based on the match. The intermediate bitmap has a resolution in a first direction (row or horizontal direction) which is greater than that of the desired output resolution and has resolution in a second direction (column or vertical direction) which is equal to that of the desired output. The appropriate block of bits is obtained by subsampling an image enhancing tile which corresponds to the matched image feature pattern. The process of matching neighborhoods and writing a subsampled image enhancing tile (i.e., block of bits) to the intermediate bitmap is repeated for each pel in the input bitmap.

Abstract: A machining method is provided for use with a smart card of the type having at least one conducting winding at some distance from the opposed faces of the card, with the end portions of the winding forming electrical connection pads for an electronic chip. According to the method, an electric potential is generated in the winding. The milling tool is made to orthogonally penetrate the card in a region of at least one of the pads, and the electric potential of the milling tool is concomitantly monitored to detect a variation in electric potential that identifies a reference position of the milling tool with respect to the card and pad. The penetration of the milling tool is continued for a predetermined travel from the reference position so as to reach a machining position. In one preferred method, the milling tool is moved parallel to the card at the depth of the machining position in order to form a cavity in the smart card. A machining apparatus for machining a cavity in a smart card is also provided.

Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue.