Abstract: A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Abstract: A security system of the type having a fixed terminal and a portable unit such as a remote control. The portable unit produces an activation signal based on active intervention by a user and a measurement signal based on the measurement of a biometrical signature of the user. A control signal is generated when the activation and measurement signals are both generated within a specified temporal window and the measured biometrical signature corresponds to that of an authorized user. Thus, there is a reduced chance of both the security system being disarmed by an ill-intentioned third party and of untimely or inadvertently disarming the system.

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node.

Abstract: A method for the repairing of defective elements of a memory in integrated circuit form, comprising redundant elements to replace defective elements, consists of the following steps:A) For each defective element detected:searching for a first non-defective redundant element by the testing of the redundant elements;assigning this first redundant element to the defective element.B) When the assigning of a redundant element to each defective element has been achieved, replacing each defective element by the assigned redundant element.

Abstract: A device for generating a high voltage includes a charge pump device that outputs a high voltage, an oscillator that supplies at least one clock signal to the charge pump device, and a regulation device. The regulation device generates a control signal to selectively stop the charge pump device based on the level of the high voltage output by the charge pump device. Additionally, the oscillator includes a shaping circuit for shaping the clock signal into a saw-tooth waveform. In a preferred embodiment, the oscillator supplies at least two clock signals to the charge pump device, and each of the clock signals has a saw-tooth waveform. A method for generating a high voltage in an integrated circuit is also provided. According to the method, at least one clock signal is generated, and the clock signal is shaped into a saw-tooth waveform. The shaped clock signal is used to generate a high voltage, and the generation of the high voltage is selectively stopped based on the level of the high voltage.

Abstract: An electrostatic discharge protection circuit for integration into an integrated circuit device. The protection circuit includes at least one transistor having a first terminal connected to an input or output terminal of the integrated circuit device, a second terminal connected to a supply line for the integrated circuit device, and a control terminal connected to ground. In a preferred embodiment, the transistor is formed by a structure that includes a substrate of a first conductivity type, a first region of a second conductivity type, a second region of the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The third region has greater conductivity than the substrate and the fourth region has greater conductivity than the first region.

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Abstract: A boosted voltage driving circuit includes an inverter circuit with positive feedback and a selective breaking circuit. The selective breaking circuit disconnects the positive feedback from the output load during an operation phase of the boosted voltage driving circuit in order to reduce energy consumption. In a preferred embodiment, the boosted voltage driving circuit is the final stage of a decoder circuit for selecting and deselecting a line or column of a memory array, and the positive feedback is disconnected during a deselection phase in which the line or column is deselected. The present invention also provides a boosted voltage driving circuit that includes first, second, and third transistors and a selective breaking circuit. The first transistor is connected between a supply voltage and an output node, the second transistor is connected between the output node and ground, and the third transistor is connected between the supply voltage and the gate of the first transistor.

Abstract: A Flash-EPROM type memory cell with a short read time and a "very low supply voltage." The memory cell has the additional advantage of using less power, therefore generating less heat and allowing a denser integrated circuit. The memory cell comprises a floating-gate transistor whose source is coupled to the drain of a selection transistor. The floating-gate transistor is in a depleted state when the memory cell is "erased." The read voltage applied to the control gate of the floating-gate transistor is substantially equal to a general supply voltage which is in the range of 1.5 volts. The gate of the selection transistor receives a bias voltage at least equal to its conduction threshold. The gate of the selection transistor can also receive a bias voltage higher than the read voltage, which will speed up the read time further. A Flash-EPROM incorporating this memory cell is also provided.

Abstract: A method for testing output connections of at least one driver circuit that drives a plasma display panel. According to the method, at least one output of the driver circuit is switched to a high level for a predetermined time period. The output of the driver circuit is switched to a low level, and the time to discharge the output of the driver circuit with a constant discharge current is measured. It is determined whether a capacitive load is connected to the output of the driver circuit based on the measured time to discharge. In one preferred method, these steps are repeated for each of the outputs of the driver circuit. A driver circuit for driving a plasma display panel is also provided. The driver circuit includes driver output stages, and means for selectively sinking a constant discharge current from the output of at least one of the driver output stages to ground.