Abstract: In one embodiment of the present invention, an apparatus for one-step flow control at a micro-channel crossing comprises a first micro-channel and a second micro-channel, a plurality of magnetic valves, and a guiding magnet. The guiding magnet produces a proximal magnetic field gradient at a location of each of the plurality of magnetic valves when an operator places the guiding magnet in a vicinity of the chip. The vicinity of the chip comprises a plurality of guiding magnet position ranges. The operator repositions guiding magnet in order to actuate the plurality of magnetic valves simultaneously. Depending on the position of the guiding magnet, the passages are blocked or unblocked to stop or let the fluid flow in a given crossing.

Abstract: In one embodiment as described in this section, an apparatus for mixing of microfluidic streams on a chip is presented, which comprises a micro-channel and a plurality of magnetic valves on the chip. A guiding magnet produces a proximal magnetic field gradient to exert a force on a bead in a cavity when placed at in a vicinity of the chip. The bead-cavity combination form a magnetic valve. In one embodiment, the mouth of the cavity is tapered so to prevent the magnetic bead from completely blocking the corresponding micro-channel section to enhance the mixing of microfluidic streams at the narrowed fluid path. In one embodiment, magnetically actuated valves direct the flow in a microfluidic system in one of several flow paths wherein the mixing characteristics of the paths are different.

Abstract: A method and system for enabling management of a plurality of messages in a communication network is provided. The method includes measuring an in-load and an out-service corresponding to a plurality of switching-nodes in the communication network. The method further includes marking at least one message in a switching-node with an Explicit Congestion Notification (ECN) to form at least one Precise ECN (PECN)-message, if at least one predefined criterion corresponding to a switching-node evaluates to true. Each PECN-message is encoded with measurements of the in-load and the out-service corresponding to the switching-node. Thereafter, one or more management functions are performed to modify egress of the plurality of messages from a source-node. The source-node transmits the plurality of messages to a destination-node through the switching-node.

Abstract: The present invention provides a method for transferring encrypted information from one storage area to other storage area wherein cryptographic data protection scheme having protection attributes are applied on the data. A crypto container having cryptographic properties represents cryptographically protected data. The attributes that have been attached to the container at the time when data is added or removed from the container determine the scheme of data protection being applied. Crypto container can be converted or serialized for storage or transmission, here the conversion spread only to the protected data parts which possibly includes crypto containers in protected form but may not the attached crypto attributes. These attributes must be stored or transmitted in another form.

Abstract: The present invention relates to a method and a system of flow control in a communication network. The method comprises determining if at least one sender buffer has a sufficient number of credits. The sufficient number of credits informs the sender buffer if the receiver buffer has an available buffer space corresponding to at least one data packet. The method further comprises transmitting the at least one data packet to at least one receiver buffer, if the at least one sender buffer has the sufficient number of credits. If the sufficient number of credits in the at least one sender buffer are absent, a data packet is transmitting speculatively to the at least one receiver buffer. If a negative acknowledgement is received for the transmitted data packet, a copy of the data packet can be retransmitted to the receiver buffer.

Abstract: A method and apparatus for providing ESD protection of an integrated circuit using a temporary conductive coating. The method deposits a temporary conductive coating upon a chip die between contacts to be protected such that a conductive path is created between contacts, provides a carrier substrate that is then bonded to the chip die and then the conductive coating is deactivated to ready the device for use. The deactivation of the conductive coating may involve physical removal of the conductive coating (or a portion thereof), oxidation of the conductive coating to form a non-conductive coating, or some other process to interrupt the conductive path between contacts. The apparatus of the invention is a chip having a temporary conductive coating deposited thereon to protect the integrated circuit from ESD events.

Abstract: A method and apparatus for facilitating reduction in successful attacks on a monitored data processing system, such as a host computer. An intrusion detection system comprises a host or application based sensor for detecting code based intrusions with a relatively low false-positive rate. Malicious code strings related to a detected intrusion are identified, extracted and forwarded to a pattern filter located in the monitored data processing system to prevent further intrusions using said malicious code strings. The malicious code strings may be forwarded to a response server for assembling sets of similar malicious code strings for which signatures are generated to permit identification of all malicious code strings contained in a set. The generated signatures are then distributed to monitored and/or monitoring systems of a protected network to prevent further intrusions using the malicious code strings and variations thereof.

Abstract: A surface adapting cap with an integrated adapting thermally conductive material on single and multi chip module provides reduced gap tolerance and hence better thermal performance of the semiconductor device which enhances the reliability of the semiconductor device. In one of the embodiments the cap is modified with an integrated, confined, and high thermal adaptive material. The membrane on this system is highly flexible. The cap is preassembled to the chip at a temperature above liquidus below curing temperature of the adaptive material. At this state, a hydrostatic pressure in the material develops due to the compression exerted from the cap to the chip and the confined volume of the buried material. This hydrostatic pressure causes the membrane to deflect and to adapt the warping and tolerances of the chip. Due to the adaptive surface the gap on each position of the chip and from chip to chip is same.

Abstract: The invention describes methods, systems and an apparatus for determining a priority value for a thread for execution on a multithreading processor system. The priority value is determined subject to a priority base rating and an application priority rating. The priority base rating represents a priority rating of the thread with regard to other threads. The application priority rating represents a priority rating of the thread from the thread's application point of view.

Abstract: A method for forming a multilevel structure on a surface by depositing a curable liquid layer on the surface; pressing a stamp having a multilevel pattern therein into the liquid layer to produce in the liquid layer a multilevel structure defined by the pattern; and, curing the liquid layer to produce a solid layer having the multilevel structure therein. Mechanical alignment may be employed to enhance optical alignment of the stamp relative to the substrate via spaced protrusions on the substrate on which the structure is to be formed and complementary recesses in the patterning of the stamp.

Abstract: An off-chip signal is provided to a differential branch-line directional coupler implemented entirely on-chip. The coupler produces differential quadrature signals, which are then buffered and applied to a quadrature mixer. The coupler is implemented entirely on-chip using microstrip transmission lines. The coupler is made up of a plurality of rings and a plurality of underpasses connecting ports of the rings, wherein each of the plurality of rings is made up of four branch lines, and each branch line having an electrical length of one-quarter wavelength at the center design frequency. Coupling between the plurality of branch lines of the rings may be varied.

Abstract: A computer-implemented method for modeling a target system includes defining a cloned constraint satisfaction problem (CSP) that characterizes the target system in terms of a set of variables and constraints applicable to the variables. The cloned CSP includes a non-predetermined number of duplicate sub-problems corresponding to instances of a repeating feature of the target system. The variables are partitioned so as to define an abstract CSP containing a subset of the variables relating to the duplicate sub-problems. The abstract CSP is solved to generate an abstract solution indicating the number of duplicate sub-problems to use in the cloned CSP. A concrete solution to the cloned CSP is found using the abstract solution.

Abstract: An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of n1 and n2 bits, respectively, such that n1<m1. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.

Abstract: A counterfeit detection method includes electronically reading a label on a desired item in a store, transmitting an item identification code encoded in the read label to an authentication unit, receiving an indication from the authentication unit whether or not the item identification code is registered to the store and if the indication is positive, generating a certificate of authenticity for the desired item.

Abstract: The present invention relates to a controller comprising: at least two input terminals, each of which is configured to receive one of at least two input signals comprising information on a positioning of a scanner relative to a reference medium, and an output terminal, which is connectable to the scanner and configured to transmit an output signal, which is used for controlling the positioning of the scanner, wherein the controller further comprises: a processing unit being operable to designate a corresponding weighting function to each of the at least two input signals, a magnitude of the corresponding weighting function being selected to be in accordance with a noise profile of the input signal to which it has been designated; the processing unit further being operable to simultaneously use the at least two input signals, each with the corresponding weighting function designated thereto, to design a transfer function of the controller for use in the production of the output signal.

Abstract: A coverage-directed test generation technique for functional design verification relies on events that are clustered according to similarities in the way that the events are stimulated in a simulation environment, not necessarily related to the semantics of the events. The set of directives generated by a coverage-directed test generation engine for each event is analyzed and evaluated for similarities with sets of directives for other events. Identified similarities in the sets of directives provide the basis for defining event clusters. Once clusters have been defined, a common set of directives for the coverage-directed test generation engine is generated that attempts to cover all events in a given cluster.

Abstract: A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.

Abstract: A Bayesian network correlating coverage data and input data to a test verification system for coverage directed test generation (CDG) of a device under test. In one embodiment, the Bayesian network is part of a CDG engine which also includes a data analyzer which analyzes coverage data from a current test run of a test verification system and from previous test runs to determine which coverage events from a coverage model have occurred therein, at what frequency and which ones have not yet occurred, a coverage model listing coverage events which define the goal of the test verification system and a task manager coupled to the data analyzer and the Bayesian network which refers to the coverage model and queries the Bayesian network to produce input data to achieve desired coverage events.

Abstract: A method for solving a constraint satisfaction problem (CSP) includes choosing a first state corresponding to a first set of values of a set of variables, and selecting a hop distance within a state space of the variables responsively to a random distance selection criterion. A second state corresponding to a second set of the values of the variables is selected, such that the second state is separated from the first state by the hop distance. Constraint costs of the first and second states are compared. If the cost of the second state is lower than the cost of the first state, the first state is redefined to correspond to the second set of the values of the variables. These steps are repeated until a solution of the CSP is found.

Abstract: A differential cascode amplifier has first and second cascode circuits, driven by two differential signal sources including input resistances. The first cascode circuit includes a first input transistor having a first collector, a first emitter, and a first base, and a first output transistor having a second collector, a second base, and a second emitter coupled to the first collector. The second cascode circuit includes a second input transistor having a third collector, a third emitter, and a third base, and a second output transistor having a fourth collector, a fourth base, and a fourth emitter coupled to the third collector. The amplifier has a first connection connecting the first base to the fourth base, and a second connection connecting the second base to the third base. This cross-connected differential cascode architecture provides doubled output bandwidth and current gain (in dB), further increasing input impedance and output swing.