Abstract: A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and second regions and having a given sustaining voltage serially connected with a capacitor. The circuit further includes means for applying between the first and second spaced apart regions a given supply voltage having a magnitude greater than the magnitude of the sustaining voltage and less than the breakdown voltage of a PN junction formed in the transistor and means including a control voltage applied to the gate electrode of the transistor for initiating current flow between the first and second spaced apart regions when the given supply voltage is applied between the first and second spaced apart regions.

Abstract: A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.

Abstract: A process is provided for making a conductive structure for a semiconductor circuit, such as a one device dynamic random access memory cell, which includes the steps of depositing a conductive layer on a surface of a semiconductor substrate having a given type conductivity spaced from a storage node, depositing a layer of polysilicon over the conductive layer, depositing a layer of photoresist over the polysilicon layer, defining an opening in the photoresist layer and implanting ions of a conductivity type opposite to that of the given type conductivity through the opening and the polysilicon layer into the semiconductor substrate to form therein a conductive pocket or region having the opposite type conductivity resulting in, e.g., a highly conductive bit/sense line of a memory cell.

Abstract: An improved voltage sensing circuit is provided which includes a pair of cross-coupled bipolar transistors coupled to a pair of signal nodes, a pair of cross-coupled field effect transistors coupled to the same pair of signal nodes and means for activating the bipolar transistors during a first period of time and then activating the field effect transistors. The bipolar transistors are preferably NPN transistors and the field effect transistors are preferably P channel transistors. The circuit may be conveniently fabricated in complementary metal oxide semiconductor (CMOS) technology.

Abstract: A semiconductor memory is described, whose word lines are divided into several partial word lines or partitions, wherein each partial word line is connected to a word switch and all word switches of a word line are selected and controlled via a first word control line and a second word control line.

Abstract: A methodology is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential and the other end of the series circuit connected to an output terminal. Each product term is arranged in parallel with other P channel device series circuits to form one half of a complete logic matrix.

Abstract: For testing substantially two-dimensional relief-structured patterns, in particular circuit boards, an optical scanning head is used which directs a light band according to the light sectioning principle at an angle .alpha. to the printed circuit board (10) and in which a linear scanning diode array (17a) is positioned in such a manner that it receives only such light as is reflected by the circuit boards whose surfaces have the nominal height h from the base plate (10). For continuously controlling the operating distance (1) between the linear diode array (17a) and the base plate (10), a pair of linear diode arrays (17b) is arranged parallel to the diode array between which the light reflected at the base plate (10) is incident if the nominal operating distance (1) has been kept and on which this light impinges if deviations of the operating distance have occurred.

Abstract: A memory array is provided which includes a common sense line to which is connected a first storage capacitor through first switching means and a second storage capacitor through second switching means, with a common word line connected to the control electrodes of the first and second switching means, a first bit line connected to a plate of the first storage capacitor and a second bit line connected to a plate of the second storage capacitor. Data is stored into or read from the first storage capacitor by selecting the common word line and the first bit line and data is stored into and read from the second storage capacitor by selecting the common word line and the second bit line, with the data from both storage capacitors being detected on the common sense line.

Abstract: A differential logic system is provided for a complete logic family which has a first switching circuit that produces a given output signal at a first output node and a second switching circuit that produces a second output signal which is the complement of that of the given output signal at a second output node. First and second clocked devices are connected from the first and second output nodes, respectively, to a voltage source, and first and second inverters are connected to the first and second output nodes, respectively. Additionally, a regenerative circuit may be connected between the first and second output nodes and the voltage source.

Abstract: A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.

Abstract: An improved device isolated by a trench formed in an N conductivity type semiconductor substrate is provided which has first and second spaced apart P conductivity type regions butted to a sidewall of the trench. An N+ doped region is disposed adjacent to the sidewall of the trench extending from the surface of the semiconductor substrate to an N+ buried region and interposed between the first and second P type conductivity regions. The dopant concentration in the N+ doped region is higher than that of the semiconductor substrate but not higher than the dopant concentration of the N+ buried region. More particularly, a lateral PNP transistor, isolated within a trench formed in an N type conductivity semiconductor substrate having an N+ buried region, has emitter and collector regions butted against a sidewall of the trench, along with the transistor's base region.

Abstract: A CMOS driver or pull up circuit is provided which includes a pull up transistor of a given conductivity type and a precharged bootstrap capacitor which discharges fully through a second transistor having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A third transistor may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.

Abstract: A method is provided for making a semiconductor device which includes the steps of forming a first insulating layer on the surface of a semiconductor layer having a given conductivity type, forming an opening in the insulating layer and forming a diffusion region of a conductivity type opposite to that of the given conductivity type at the surface of the semiconductor layer to provide a P-N junction below the surface of the semiconductor layer. A trench is then formed along a given axis in the semiconductor layer having a sidewall passing through the opening and through the P-N junction. A second layer of insulation is formed on the sidewall of the trench, on the first insulating layer and through the opening onto the diffusion region. The second layer of insulation is etched in the direction of the given axis until substantially all of the second layer of the insulation is removed from the opening, and an electrical contact is formed on the diffusion region within the opening.

Abstract: A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/sense line diffusion region.

Abstract: A very simple process is provided, with reduced processing time, for making a CMOS structure using a single polysilicon, or other refractory metal, layer which includes forming a thin gate oxide on both N and P type semiconductor layers of a common substrate, forming a gate electrode simultaneously on the N type and on the P type layers and selectively implanting an N type impurity to form N+ source and drain regions in the P type layer. The semiconductor layers are then oxidized to form substantially thicker oxide, such a silicon dioxide, adjacent to the sides of the gate electrode over the P type layer than the thickness of the oxide adjacent to the sides of the gate electrode over the N type layer. Without using a mask, a P type impurity is implanted into the N type layer to form P+ source and drain regions.

Abstract: This invention provides an amplifier circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The amplifier circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the amplifier without the high write voltages destroying the high performance first and second transistors.

Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

Abstract: A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.

Abstract: A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line.

Abstract: A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region.