Abstract: A memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures.

Abstract: An arrangement which provides for storing a single lookup/bypass bit with each pixel stored in a frame buffer to indicate whether the color format used to display that pixel on the output display is to use the lookup tables, and for storing an indication apart from the frame buffer which to indicate the decode format for the pixels stored in the frame buffer and retrieved for display by programs providing graphics output in different color formats. The arrangement allows fifteen bit color formats to be stored in standard sized frame buffers without the addition of memory devices.

Abstract: A digital system which uses an arrangement of one or more parallel FIFO buffers in which each FIFO buffer handles data from only one application program at any time. In order to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer, each FIFO buffer includes a flow control register which must be read by the processing unit running the application before writing data to an input/output device. The register stores a value which indicates the amount of space available in the FIFO buffer to which data may be written. Reading this register tells the application program how much data may be written without running the risk of overflowing the data storage area which the input/output device has available.

Abstract: A method of processing a digital input image having a plurality of scan lines of pixel data into an interpolated digital output image by interpolating the pixel data in each scan line of the digital input image and replicating the pixel data in the slow scan direction to provide a plurality of scan lines interpolated in the fast scan direction, calculating slow scan direction interpolation coefficients for scan lines to be interpolated in the interpolated output image, storing the interpolated scan lines using the storage typically used for the display image, interpolating selected scan lines which have been stored using selected existing scan lines to produce scan lines interpolated in the slow scan direction of the interpolated output image, and writing scan lines interpolated in the slow scan direction in place of scan lines selected for interpolation in the output image.

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command.

Abstract: A DMA controller which responds without operating system intervention to virtual addresses provided by application programs, and a memory management unit for providing translations between physical addresses of input/output devices and addresses on a system input/output bus for data transferred by the DMA controller.

Abstract: Apparatus for transferring commands over a system transmission path between first and second components in a digital data system including a first-in first-out circuit having a plurality of stages arranged in the system transmission path, circuitry for generating a first signal to indicate that a component to which a command in the FIFO circuit is directed is unable to handle an operation commanded, and a delay circuit responsive to the first signal for causing the generation of an interrupt request signal after a preselected time.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, and additional hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the hardware for translating the input/output address to a physical address space of an input/output device.

Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, circuitry for determining from a command an application program which has initiated a command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer at any time.

Abstract: An ordered dithering process by using different sets of dithering patterns for different color components of the source pixel color instead of using the same set of patterns. The sets of dithered patterns are designed in a way that variations in intensity due to dithering of some color components are partially or fully compensated by variations in intensity due to dithering of other color components.

Abstract: An arrangement which provides hardware at the game port to provide a direct analog-to-digital conversion of input signals provided by the directional input signals of a joystick without involving the central processing unit in the determination. By determining at the game port the input values, the central processing unit need not have its interrupts disabled, and games may easily function with other application programs in a multi-tasking operating system.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.

Abstract: A system which uses an arrangement of FIFO buffers which include circuitry to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer. Each FIFO buffer includes a flow control register which stores a value which indicates the amount of space available in the FIFO to which data may be written. In order to allow for situations in which data is available at a FIFO buffer which cannot be immediately utilized for some reason, an overflow storage area is provided for storing data transferred to the FIFO buffer in excess of the number of stages of the FIFO circuit which are available to store data. The flow control circuitry also includes circuitry for assuring that data which is placed in the overflow storage area is handled in the appropriate sequence.

Abstract: Apparatus and a method by which an application program writing a series of commands to a single destination on an input/output bus increments the addresses to which the commands are addressed as the commands are written so that the commands may be transferred utilizing the burst mode of the input/output bus, and the device receiving the data decodes a large number of sequential addresses to the same destination so that the input/output device transfers all of the commands in the sequence of addresses to the single destination.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, and apparatus for handling a failure to provide an address translation.

Abstract: Apparatus for emulating input/output devices on an ISA bus using input/output devices on a local bus which includes circuitry for snooping on the bus to capture commands sent to input/output devices the functions of which are to be emulated, circuitry for storing those commands, circuitry for generating new commands in response to the commands which are stored, and circuitry for generating output signals in response to the new commands which output signals replace the output signals produced by the input/output devices on an ISA bus.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command. Context switching is effected in response to commands from unprivileged application programs without involving the operating system or trusted code.

Abstract: A hardware encoding circuit which generates a code value unique to a particular computer, stores a password unique to an application program and to the particular computer, tests the stored password against a verification value generated by the hardware encoding program each time the application program is run, and generates an error signal if the stored password and the verification value do not match.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including a circuit which responds to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address of an input/output device and transferring the command to the physical address of an input/output device, a translation table which responds to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, each selection of a safe translation being accomplished using an arbitrary name originally provided by the unprivileged application program; and a database of data structures which individually include a physical address of an input/output device and can be copied and named by application programs to provide safe translation for storage in the translation t