Abstract: A digital pixel sensor-based modular digital imaging system includes several integrated circuit modules. At least one module includes an integrated circuit die having a digital pixel sensor array and a frame buffer, and at least one module includes an integrated circuit die having control circuitry and/or I/O circuitry. In certain embodiments all component modules are generally the same; in other embodiments the component modules include different integrated circuits that perform different functions. A higher pixel count imaging system may be made by disposing several component modules having lower pixel count digital pixel sensor arrays adjacent one another.

Abstract: An image sensor having a circuit to recover photo-generated charge and to apply it to reduce consumption of power from a power supply (e.g., an external battery). In one embodiment (e.g., FIG. 4), the image sensor has at least one light-sensing photoelement implemented in an integrated circuit and adapted to be powered by a power supply, other circuitry that consumes power during a standby operating mode for the image sensor, and a circuit configured to selectively connect the photoelement to the power-consuming circuitry. During the image sensor's standby mode, the photoelement is configured to supply at least a portion of the standby current to the power consuming circuitry. In another embodiment (e.g., FIG. 3), the image sensor has a storage device (e.g., a capacitor), and a circuit configured to selectively connect the storage device to the photoelement or to the power-consuming circuitry.

Abstract: A pre-distorter pre-distorts an input signal prior to being applied to an amplifier in order to reduce spurious emissions in the resulting amplified signal. The pre-distorter implements an inverted version of a model of the amplifier that models both the frequency independent (FI) characteristics of the amplifier as well as the frequency-independent (FD) characteristics of the amplifier. Techniques and architectures are presented for (1) generating and updating the model, (2) inverting the model, and (3) updating the inverted model.

Abstract: An imput signal is provided in polar format comprising an amplitude component (210) and a phase component (212). The amplitude component (210) is supplied to a pulse width modulator (219) which derives pulse width modulated (PWM) signal. The PWM signal is used to control a switch (224) which modulates the phase component (212). The modulated phase component (212) is amplified at (216). The output of amplifier (216) has a desired envelope, as dictated by the PWM signal, whose characteristics are, in turn, derived from the amplitude component (210). Either or both of the amplitude component (210) and the phase component (212) can be predistorted (226, 218).

Abstract: Signal handling equipment, such as a high power amplifier, is implemented with feed-forward compensation circuitry that adjusts the effective operation of the equipment (e.g., linearizes the amplifier). The compensation circuitry includes (i) a nulling loop, which generates an error signal based on the output from the amplifier, and (ii) an error loop, which generates, based on the error signal, a feed-forward compensation signal that is added to the output of the amplifier. The compensation circuitry is tuned by tuning the nulling loop and then iteratively tuning the error loop based on data generated by perturbing the tuning of the nulling loop. In one implementation, data corresponding to the amplitude of the output signal is analyzed to generate metric values that are used to iteratively adjust the tuning of the error loop.

Abstract: The signal generated by a high-power amplifier (HPA) operating in its non-linear region is linearized by an amplifier circuit using feed-forward compensation in which an auxiliary channel relies on a model of the HPA to generate an auxiliary signal that is combined with the HPA output to generate an amplified linearized output signal. The amplifier circuit may be implemented with a pre-distorter in the main amplifier channel to linearize the HPA using both pre-compensation and feed-forward compensation. Using the HPA model in the auxiliary channel enables the auxiliary signal to be generated without directly relying on the HPA output. This enables the amplifier circuit to be implemented without having to delay the high-power HPA output signal prior to being synchronously combined with the auxiliary signal. In preferred embodiments, the auxiliary channel signal is generated using a relatively low-power amplifier operating in its linear region.

Abstract: An automatic gain control (AGC) circuit for an RF amplifier (or other type of signal-processing module) has a single, switched, RF detector that selectively detects the instantaneous power level of either the sampled RF input signal or the sampled (and optionally attenuated) RF output signal. A processor uses the detected input and output power levels to generate control signals for a variable (e.g., voltage-controlled) attenuator that attenuates the RF input signal prior to being applied to the input of the RF amplifier. The processor is designed (e.g., programmed) to control the variable attenuator to maintain a constant gain between the input and output terminals of the AGC circuit. In addition to this closed-loop mode of operation, the AGC circuit may also have a temperature sensor, where the processor controls the variable attenuator in an open-loop mode of operation based on the temperature of the RF amplifier.

Abstract: A discrete multi-tone communication system having a selected remote end terminal that senses data transmission activity on the discrete multi-tone communication channel. The selected remote end terminal transmits data when no data transmission activity is sensed. The discrete multi-tone system allows a plurality of remote end terminals to be connected together at a node that in turn is connected to the central office.

Abstract: A first transceiver transmits a set of test levels to a second transceiver as a signal through a communication channel as encoded samples and subjected to one or more of a plurality of line encoding algorithms. An information channel is superimposed in the signal transmitted through the communication channel. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. Encoded samples representing the transmitted test levels are reconstructed by the second transceiver in accordance with the one or more detected line encoding algorithms, the encoded samples for each of the set of test levels packed into a corresponding sample cell.

Abstract: A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of conventional placed-switch, switch-box, and pseudo-arc connections. A hidden-switch connection between two functional elements in the PLD is represented in graphical displays generated by the programming tool as a curve (e.g., a diagonal straight line) from a jumper wire on the first functional element to another jumper wire on the second functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to an pin of the corresponding functional element and unconnected at the other end. A programming tool that supports hidden-switch connections can be used to program FPGAs and other PLDs having architectures that were not previously supported by conventional programming tools that do not support hidden-switch connections.

Abstract: A method and apparatus are disclosed for reducing the computational complexity of the RSSE technique. The apparatus and associated method does not assume that the signal energy of a pulse that has gone through a channel is always concentrated primarily in the initial taps, as is true for a minimum phase channel. The present invention, however, recognizes that the signal energy is often concentrated in just a few channel coefficients, with the remaining channel coefficients being close to zero. A receiver apparatus and associated method is disclosed for reducing the number of channel coefficients to be processed with a high complexity cancellation algorithm from L to V+K which contain the majority of the signal energy, while processing the L−(K+V) non-selected coefficients with a lower complexity algorithm. By only processing the intersymbol interference caused by a reduced number of channel coefficients (i.e.

Abstract: A system for deriving multiple channels from four-wire residential telephone wiring. The invention provides two voice channels and two, or more, data channels on common residential telephone wiring. The voice channels occupy a normal telephone bandwidth, in the range of approximately zero Hz to 3500 Hz. With this channel placement, ordinary telephonic devices can use the channels, without a requirement of frequency-shifting. Above these voice-channel frequencies, data channels are provided, for internal communication within the residence.

Abstract: An enclosure for electronic components has a chassis, a cover mountable to the chassis, and a face plate mountable to the chassis/cover sub-assembly. The top side of the cover has a generally U-shaped groove running along three sides to receive a friction-fitted gasket that forms a portion of the environmental seal for the enclosure. Each end of the groove has a J-shaped portion within which the gasket loops back on itself. The bottom of each J-shaped portion is open on the cover's front side, such that the side of the gasket will protrude beyond the front side of the chassis/cover sub-assembly, thereby providing a portion of the seal when the face plate is mounted onto the chassis/cover sub-assembly. The J-shaped portions account for contraction of the gasket due to strain relief after the gasket is placed in the groove and provide increased frictional force that further inhibits such strain relief.

Abstract: An integrated image sensor having a conditioned top silicon oxide layer and/or one or more additional insulating layers/structures to reduce optical and/or electrical noise. The image sensor has an array of one or more pixels, each pixel having a photoelement formed on a substrate and configured to generate an electrical signal in response to incident light, and associated circuitry formed on the substrate and configured to process the electrical signal generated in the photoelement. In one embodiment, a portion of a top insulating layer in the integrated image sensor corresponding to each photoelement has a thickness different from the thickness of a portion of the top insulating layer corresponding to its associated circuitry to inhibit the flow of light between the associated circuitry and the photoelement and/or between the pixel and an adjacent pixel in the array.

Abstract: An imaging system with built-in diagnostics and preferably implemented as an integrated system-on-a-chip (SOC) imaging system. According to one implementation of the present invention, the imaging system can be operated in two operating modes: a normal operating mode and a special diagnostic mode. While running in the diagnostic mode, the imaging system can be configured to detect manufacturing defects. The imaging system can be further configured to compensate for certain types of manufacturing defects. While running in the diagnostic mode, the imaging system (1) identifies pixels that function incorrectly and (2) creates a record of such pixels. In the normal operating mode, the imaging system can use the record to compensate for the missing or incorrect data from these defective pixels during real-time image processing. The present invention simplifies testing of imaging systems and/or image sensors. It also increases manufacturing yield and, therefore, results in lower per-unit manufacturing cost.

Abstract: A method and apparatus for estimating the timing position of data bursts received in a data stream, where each data burst includes a number of bits comprising a training sequence in a fixed location. The receiver includes circuitry for estimating the timing position of the data bursts received in the data stream. For each of the first N received data bursts, the receiver estimates a plurality of timing locations of the training sequence, correlates the training sequence for each estimated timing location, and determines the timing location associated with the highest correlation value. The receiver then determines the average timing location of the highest correlation values for each of the first N data bursts. For the next M data bursts the receiver estimates the timing location of each data burst based on the average timing location for the first N data bursts.

Abstract: The input signal (110) to a non-linear amplifier (112) is predistorted by injecting a correction signal at coupler (124). To generate the correction signal, a sample of the input signal is amplified using amplifier (130) which has substantially the same distortion generating characteristics as amplifier (112). The output of amplifier (130) is sampled, and the main tone energy is removed at (138), leaving the correction signal for injection to the main signal path. The main portion of the output of amplifier (130) is added coherently to the output of amplifier (112) to enhance efficiency. The correction signal can be manipulated to correct distortion in the output of combiner (152) due to the main portion of the output of amplifier (130).

Abstract: A first transceiver transmits a set of test levels to a second transceiver through a communication channel in which one or more types of companding laws are used for line encoding. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. A decision metric is also generated from the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws. The second transceiver then compares a combination of the set of test levels that is received from the communication channel with the decision metric.

Abstract: A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

Abstract: A counter sequence is mapped with an interleaving algorithm Both the sequence and mapped sequence of values are associated with values in a block of data values and a corresponding block of interleaved values. For a receiver, the mapped counter sequence is employed to generate a sequence of addresses corresponding to of the interleaved block in a buffer. The counter provides a sequence of address values associated with the original sequence of data values before interleaving. Memory addresses for storing the data values in the interleaved block to reconstruct the original block are assigned based on the counter sequence and the mapped counter sequence of values.