Abstract: An electronic video dental camera is provided which overcomes the disadvantages of both prior art dental mirrors, endoscopes, and video endoscopes. The electronic video dental camera is readily manipulated by dentists who are familiar with the manipulation of dental mirrors. Such an electronic video dental camera includes a handle to be held the user, and a camera head located at the distal end of the handle, with the camera head being formed at an angle to the handle, as in prior art dental mirrors. One embodiment includes provision for the flow of a selected fluid in order to defog and/or clean the camera lens. In one embodiment, the camera head includes light sources for illuminating the area to be viewed. In one embodiment, the handle of the dental camera includes means for transporting all appropriate signals and fluids to and from the camera head, and, if desired, valves and switching means located on the handle for controlling such communication to the camera head.

Abstract: An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

Abstract: An improved focus and tracking error detection circuit for an optical disk servo system. The circuit calculates the logarithm of the signal from each of at least a pair of photodetectors. The difference between two logarithmic signals is then determined to give an error signal. The invention takes advantage of the property of logarithms that the difference between two logarithmic signals is equivalent to the logarithm of the ratio of the two signals. Accordingly, the error signal is a ratio, rather than an absolute difference signal, and is thus insensitive to variations which affect both signals. In addition, the logarithmic circuits inherently minimize variations which affect the photodetectors unequally by performing an AGC-type function. The error signal is inhibited during a write pulse to the laser to prevent saturation of the amplifiers. An automatic, periodic offset adjustment is provided by turning off the laser and varying an offset voltage until the error signal is zero.

Abstract: An ECL input buffer is particularly well-suited for use with logic arrays where a large amount of current must be sunk by the row line, for example, when vertical fuse devices are used in an AND array. The input buffer provides means for pulling down the row line such that the entire amount of current sunk by the input buffer from the row line need not pass through a current source, thereby minimizing current consumption of the input buffer. A pull down current source is used which causes a pull down transistor to turn on, thereby pulling down the row line while requiring only the base current of the pull down transistor to be consumed by the current source. A pull up device is utilized and means are included for insuring that the pull up and pull down devices are not both turned on simultaneously, thereby preventing a current spike through the pull up and pull down means.

Abstract: A novel self-timing qualification channel structure is taught, suitable for use in detecting data from a magnetic disk or other storage medium. A timing comparator is used in addition to a hysteresis comparator in order to detect when the true peak of the input signal is about to occur. The timing comparator output determines when signal qualification by the hysteresis comparator is to occur. The timing comparator only allows signal qualification to occur just prior to the true peak in the input signal. Because of this, the risk of falsely detecting off track noise or noise in the shoulder region is greatly reduced. In one embodiment, the timing comparator operates without the need for additional external components by utilizing the existing channel filter. Thus, the channel filter serves two purposes: to filter the channel input signal prior to detection and to provide delay for the timing comparator.

Abstract: A novel sense amplifier is taught which minimizes power consumption by causing selected current sources to conduct current only when an input signal of a selected state is present. The speed of the circuit is fast because capacitance on the critical nodes is minimized by connection of fewer transistors to the critical nodes, as compared with the prior art.

Abstract: During the arrival phase of long seeks, e.g. the last six tracks of a seek, and during the entirety of relatively short seeks, e.g. seeks of less than 256 tracks, position mode servo control is employed by locking an actual tracking error feedback signal to a microprocessor-synthesized reference tracking error signal. The position mode servo feedback loop employs a parallel combination of a synchronous demodulator and a phase-frequency detector to achieve good locking performance over the entire frequency spectrum of the synthesized reference tracking error signal.

Abstract: A method and structure is provided to test for leakage currents in a fuse array. A diode is connected to each column in the array in order to isolate the column from the test circuitry during normal operation of the device. During testing, current is fed through a diode to a column, and the corresponding leakage current is measured. In one embodiment, the anodes of each diode are connected in common to a single test point, and the total leakage current from the entire fuse array is measured simultaneously. In another embodiment, addressing means are used to selectively address a desired one of the test diodes and thus a corresponding one of the columns such that leakage current through a single column.

Abstract: In accordance with the teachings of this invention, a novel auto-zero comparator is provided in which the on resistance of MOS switches serving as transfer gates used in the auto-zero mode to connect the output lead to the input lead is minimized without the need to increase the width to length ratio of the MOS switches. In accordance with the teachings of this invention, the on resistance of the transfer gates is reduced by reducing the threshold voltage of the transfer gates, which in turn is accomplished by making the bulk to source voltage of the transfer gates equal to zero. This is accomplished by utilizing a replica bias circuit which, during the auto-zero mode, replicates the voltage on the source of the transfer gates and applies this replica bias voltage to the bulk of the transfer gates.

Abstract: A novel output buffer is described which includes a plurality of pull up transistors connected in parallel and/or a plurality of pull down transistors connected in parallel. A desired amount of resistance is included in the path connecting the gates of the pull up transistors, and in the path connecting the gates of the pull down transistors, thereby providing a distributed RC network causing pull up and pull down transistors to turn on in sequence. This is designed to keep the rate of change of the pull up and pull down current constant, thus reducing ground and Vcc bounce. In another embodiment, a single pull up transistor and/or a single pull down transistor is used. The single transistors have a relatively high gate resistance such that along the channel width of the transistor, the gate capacitance and the gate resistance operates as a distributed RC network.

Abstract: A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Abstract: A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.

Abstract: A vertical trench etched several microns deep into the silicon extending into a buried diffusion region is used to confine a vertical interconnect element. This element can be a high resistivity undoped polycrystalline silicon load resistor, a medium resistivity doped polycrystalline silicon load resistor, or a low resistivity interconnect to the buried diffusion region. This new structure can be used in compact and scalable MOS and bipolar inverters and in bistable memory storage cells.

Abstract: Means is provided for use in an optical character recognition system to narrow the possible characters associated with a given unknown input character, primarily based upon subline information. This means also serves to add to the possibility set additional possible characters, and to determine point sizes for each character. In the event that the subline information provided is erroneous, the subline information is corrected.

Abstract: A novel multistep flash analog to digital converter is taught, including a voltage estimator which quickly provides a rough estimate of the analog input signal. This rough estimate is used to select appropriate reference voltage tap points for use in the first flash conversion. This first flash conversion, together with the voltage estimate, provides the most significant bits of the digital output word. A digital to analog converter is used to provide a residual voltage which is then converted by a second operation of the flash converter, thereby providing the least significant bits of the digital output word. In one embodiment, the voltage estimate is performed at the same time that the analog input signal is sampled by the flash converter in preparation for the first flash conversion. Therefore, speed of operation is not degraded by the addition of the voltage estimator.

Abstract: A device to measure intermodulation products of a receiver of at least two electromagnetic signals of different frequencies comprises at least two channels for the transmission of the signals of different frequencies and one reflective reception channel connected to an apparatus for the measurement of intermodulation products. The reception channel enables the transfer of signals in a frequency band centered on the reception frequency band of the receiver. A reflective reception multiplexer/demultiplexer with directional filters provides for the interconnection of the two transmission channels of the reflective reception channel of the receiver.

Abstract: A vehicular early warning system includes one or more of the following modules: An accelerator pedal pressure sensor for providing an early warning braking signal. If desired, this element also functions as a backup brake light system totally independent of the standard brake lights. A deceleration sensor which reads either intake manifold vacuum or accelerator linkage postion. This sensor lights an amber lamp providing a deceleration warning signal. A brake pedal pressure sensor system including two sensors. The first serves as the standard brake sensor. The second sensor signals high brake pressure, indicating heavy braking. A low velocity speedometer sensor, which automatically triggers a warning light as a vehicle comes to a stop.

Abstract: In accordance with the teachings of this invention, a novel electrical interconnect structure is taught, together with the process for forming this structure. In accodance with the teachings of this invention, this structure includes an electrical interconnect layer which is formed on a grooved portion of the surface of a semiconductor device. Thus, the effective cross-sectional area of the electrical interconnect layer is increased because the electrical interconnect material is formed into the grooves. With the thickness of the electrical interconnect layer thus increased as compared with the thickness of prior art electrical interconnect layers, the sheet resistance of the electrical interconnect layer of this invention is reduced over the sheet resistance of prior art electrical interconnect layers. With a lower sheet resistance, a given length of electrical interconnect can be formed of the same resistance as in the prior art with a smaller width.

Abstract: A method and structure is provided whereby contaminated soil is decontaminated in situ by the extraction of vapor from the soil and subsequent destruction of the contaminants contained in the interstitial fluid of the soil by processing the fluid through an internal combustion engine or other suitable combustion means. To achieve this purpose, the invention is provided with a means of conducting the fluid from the soil to a manifold system.

Abstract: In accordance with the teachings of this invention, resistors are fabricated in semiconductor devices utilizing a layer of semiconductor material having a preselected resistivity. Means are provided for electrically isolating the semiconductor region from the regions located beneath, and isolation to adjacent regions is provided by forming a groove. Resistance value of a particular resistor fabricated in accordance with the teachings of this invention is dependent, in a coarse fashion, on the length and width of the resistor, as well as the resistivity of the semiconductor material used to fabricate the resistor. However, the final resistance value is determined by the diffusion of high concentration isolation dopants which serve to accurately control the effective cross-sectional area of the resistor.