Abstract: A system and method for receiving and validating user input for a computer resource entered into a computing system or network, and distinguishing valid and invalid portions of the user input. The invalid resource identifier, which ranges from a least specific portion to a most specific portion, is partitioned into a plurality of fields. At least one of the fields corresponding to the most specific portion of the invalid resource identifier is removed from the invalid resource identifier to create a modified resource identifier, wherein the modified resource identifier is used to attempt to access a higher level computer resource. The fields corresponding to the most specific portion of the resource identifier are removed until the modified resource identifier proves to be a valid resource identifier which can access a computer resource.

Abstract: A memory architecture and method of partitioning a computer memory. The architecture includes a cache section, a setup table, and a compressed storage, all of which are partitioned from a computer memory. The cache section is used for storing uncompressed data and is a fast access memory for data which is frequently referenced. The compressed storage is used for storing compressed data. The setup table is used for specifying locations of compressed data stored within the compressed storage. A high speed uncompressed cache directory is coupled to the memory for determining if data is stored in the cache section or compressed storage and for locating data in the cache.

Abstract: An address verification system for providing address error detection whether the error originates at the address generation circuitry, the address transmission path, or the address receiving circuitry. Multiple address generation circuits which simultaneously generate equivalent addresses each have associated parity generation circuits to provide parity bits for its associated address. Monitoring for unequal parity bits generated by the multiple parity generation circuits allows detection of address generation errors. Predetermined address parity bits for each potential address to be sent to the address-receiving circuitry are stored at the address-receiving circuitry to be compared to the parity bits issued by the multiple parity generation circuits.

Abstract: A self-timing clock generator for use with a precharged Static Random Access Memory (SRAM). The invention asynchronously switches the memory clock pulse to a precharge signal upon recognition of completion of a memory access cycle. Recognition of completion of the memory access cycle is performed in one of two ways. The first method monitors for the existence of a preprogrammed memory-completion bit which becomes active at the same time that read or write data becomes valid at the data outputs. The second method monitors for the existence of a memory-completion bit generated through the use of an odd parity generator. An alternate clocking method is provided to bypass the asynchronous self-timing clock generator, and to allow for synchronous clocking of the precharged SRAM. An external clocking method is also provided to directly clock the precharged SRAM.

Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.

Abstract: A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired.

Abstract: A system of terminating a differential transmission line is described, where the differential transmitter and differential receiver are supplied by different power sources. The termination circuit comprises an unbalanced voltage divider pair, a connection to the receiver's voltage source, an adjustable threshold voltage, and circuitry to reduce power consumption. An unbalanced voltage divider pair provides matched termination impedances, and prevents undesired receiver output upon loss of transmitter signals. The voltage supplying the unbalanced voltage divider pair provides a voltage differential at the receiver inputs upon loss of the transmitter power source. An adjustable threshold voltage provides the minimum receiver input threshold voltage on which the transmitter signals can be superimposed. Power consumption is reduced through the use of a current limiter, which is coupled with a high pass filter to maintain the characteristic impedance of the transmission line during high frequency transmission.