Abstract: A low power mode and feedback arrangement for a switching power converter. Two or more main power switches, such as transistors, transfer energy from a supply to load by their opening and closing. When the load requires a relatively low power level, this condition is detected. In response, one or more of the transistor switches is disabled from switching and the reduced power requirements of the load are handled by the remaining one or more transistor switches. As a result, switching losses are reduced. This is because parasitic gate capacitance and on-resistance associated with the disabled switches no longer consume power from the power source. The invention provides significant efficiency advantages during periods when the load draws a low level of power. This is especially useful for battery-powered devices which may operate in a low power mode for extended periods of time, such as standby mode as in a portable telephone.

Abstract: Provided are a method and apparatus configured to enable the preservation and recovery of in-progress developments and changes as they are made in a system for development of content in the event of a process or system failure. The in-progress data developments and changes may be preserved while they are created, and may then be retrieved and recovered after the system or process is recovered. The in-progress data developments and changes may be preserved while they are created, and may then be retrieved and recovered after the system or process is recovered. In one embodiment, the cache memory contents are mirrored into a memory-mapped file, providing a redundant location for cache data. In the event of a failure, the mirrored cache information is available for recovery from a file. This extra cache location can be filled and flushed as needed by the system as the cache data is stored to disk or other memory location, obviating its preservation.

Abstract: The present invention is directed toward methods and apparatus for data packet transmission scheduling using a partitioned scheduling heap data structure. The scheduling heap data structure has a plurality of levels for storing scheduling values for data packets according to their relative priorities. A highest level in the heap has a single position and each succeeding lower level has twice the number of positions as the preceding level. The data structure may be adapted to store a plurality of logical heaps within the heap data structure by assigning a highest level of each logical heap to a level in the heap data structure that is lower than the highest level. Thus, a single physical memory may be adapted to store plural logical heaps. This is useful because a single physical memory can be adapted to prioritize packets of various different transmission protocols and speeds.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: A low power mode and feedback arrangement for a switching power converter. Two or more main power switches, such as transistors, transfer energy from a supply to load by their opening and closing. When the load requires a relatively low power level, this condition is detected. In response, one or more of the transistor switches is disabled from switching and the reduced power requirements of the load are handled by the remaining one or more transistor switches. As a result, switching losses are reduced. This is because parasitic gate capacitance and on-resistance associated with the disabled switches no longer consume power from the power source. The invention provides significant efficiency advantages during periods when the load draws a low level of power. This is especially useful for battery-powered devices which may operate in a low power mode for extended periods of time, such as standby mode as in a portable telephone.

Abstract: A spectral shaping PCM modem communication system uses a symbol encoder to encode a data bit stream into a PCM symbol stream. A plurality of different frames are formed from the PCM symbol stream. Performance metrics are computed for each possible frame and its inversion so a decision can be made in order to select a most desirable frame and inversion. Delays are injected in the data flow to allow a look-ahead and thus provide for better frame selection and inversion decisions. A channel multiplexer combines decision bits and output frames to form encoded output frames that are fed to a digital channel connected to a telephone network wherein they are converted to analog signal. A corresponding decoder converts analog signals from the telephone network to digital signals. A timing recovery and equalization means corrects sample timing and removes inter-symbol interference effects introduced by telephone networks.

Abstract: A device for use in a modem configuration that enables the transfer of data from a host signal processor (HSP) to an A/D-D/A converter or CODEC with less data loss, with low noise and that can send data at varying carrier frequencies without changing the size of the buffers. The device further allows for data transfer that is flexible with any given modulation scheme, carrier frequency or baud frequency to conform with the V.34, V90, as well as prior and subsequent recommendations. The device further includes a counter for counting the number of data samples transferred between the CODEC and the HSP and for alerting the HSP to avoid an overflow condition. The counter is further configured to count beyond the physical size of the buffer in order to simplify operation in an overflow condition. A transmit buffer is included for transferring data from the HSP to the CODEC.