Patents Represented by Attorney, Agent or Law Firm Stuart H. Mayer
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Patent number: 6834141Abstract: A filtering device such as an optical interleaver/deinterleaver includes first and second optical couplers each having two inputs and two outputs. The inputs of the first coupler are adapted to receive input optical signals to be filtered and the outputs of the second coupler are adapted to provide filtered output optical signals. A first optical waveguide optically couples a first output of the first coupler to a first input of the second coupler. A second optical waveguide optically couples a second output of the first coupler to a second input of the second coupler. The filtering device also includes an optical resonator and a third optical coupler optically coupling the optical resonator to the second optical waveguide.Type: GrantFiled: October 22, 2002Date of Patent: December 21, 2004Assignee: Wavesplitter Technologies, Inc.Inventor: Erkin Sidick
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Patent number: 6825764Abstract: A portable proximity alert detector is provided for a user to determine when at least one companion comes within a predetermined range of the user. The device includes a receiving portion for wirelessly receiving a first signal encoded with a code identifying a companion and a transmitting portion for wirelessly transmitting a second signal encoded with a user identifying code. The device also includes a processor, a modulator operationally coupling the processor to the transmitting portion for modulating the user identifying code, and a demodulator operationally coupling the processor to the receiving portion for demodulating the companion identifying code. A first memory segment is operationally coupled to the processor for storing companion identifying codes received by the receiving portion. A second memory segment is operationally coupled to the processor for storing companion identifying codes of companions whom the user desires to contact.Type: GrantFiled: March 28, 2003Date of Patent: November 30, 2004Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: Anthony Capobianco, John Timothy Nolan
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Patent number: 6794251Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon.Type: GrantFiled: April 16, 2003Date of Patent: September 21, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6782157Abstract: The abstract is amended to read, “An inventive method and apparatus is provided by a bidirectional optical 1×2 device formed by a cascade of three optical 2×2 devices. Each 2×2 device is bidirectional where optical signals propagate through the 2×2 device in the forward and backward directions simultaneously. The demultiplexing and multiplexing occur simultaneously to thereby perform bidirectional 1×2 optical demultiplexing and 2×1 optical multiplexing in the 1×2 device.Type: GrantFiled: January 2, 2002Date of Patent: August 24, 2004Assignee: Wavesplitter Technologies, Inc.Inventors: Huali Ariel Luo, Kevin Sullivan
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Patent number: 6781196Abstract: A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.Type: GrantFiled: March 11, 2002Date of Patent: August 24, 2004Assignee: General Semiconductor, Inc.Inventors: Koon Chong So, Fwu-Iuan Hshieh, Yan Man Tsui
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Patent number: 6770548Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.Type: GrantFiled: May 5, 2003Date of Patent: August 3, 2004Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Koon Chong So
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Patent number: 6768843Abstract: A cascaded interleaver includes at least three two-stage Fourier filters. A first of the Fourier filters includes first and second waveguides such that the first waveguide has a longer optical path length than the second waveguide. A second of the Fourier filters includes third and fourth waveguides such that the third waveguide has a longer optical path length than the fourth waveguide. A third of the Fourier filters has fifth and sixth waveguides such that the fifth waveguide has a longer optical path length than the sixth waveguide. The third waveguide has an input coupled to an output of the first waveguide and the fifth waveguide has an input coupled to an output of the second waveguide. At least one of the Fourier filters include at least three couplers alternating with a delay path between adjacent ones of the couplers. A second of the couplers is of an order different from a first and third of the couplers.Type: GrantFiled: August 16, 2002Date of Patent: July 27, 2004Assignee: Wavesplitter Technologies, Inc.Inventor: Erkin Sidick
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Patent number: 6750104Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. The trench is etched using an etchant gas that also serves as a dopant source for the formation of the doped column. For example, if a p-type dopant such as boron is desired, BCl3 may be used as the etchant gas. Alternatively, if an n-type dopant such as phosphorus is required, PH3 may be used as the etchant gas. The dopant present in the gas is incorporated into the silicon defining the surfaces of the trench. This dopant is subsequently diffused to form the doped column surrounding the trench.Type: GrantFiled: December 31, 2001Date of Patent: June 15, 2004Assignee: General Semiconductor, Inc.Inventors: Richard A. Blanchard, Fwu-Iuan Hshieh
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Patent number: 6740951Abstract: A Schottky rectifier includes a semiconductor structure having first and second opposing faces each extending to define an active semiconductor region and a termination semiconductor region. The semiconductor structure includes a cathode region of the first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face. The drift region has a lower net doping concentration than that of the cathode region. A plurality of trenches extends from the second face into the semiconductor structure and defines a plurality of mesas within the semiconductor structure. At least one of the trenches is located in each of the active and the termination semiconductor regions. A first insulating region is located adjacent the semiconductor structure in the plurality of trenches. A second insulating region electrically isolates the active semiconductor region from the termination semiconductor region.Type: GrantFiled: May 22, 2001Date of Patent: May 25, 2004Assignee: General Semiconductor, Inc.Inventors: Yan Man Tsui, Fwu-Iuan Hshieh, Koon Chong So
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Patent number: 6713351Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.Type: GrantFiled: March 28, 2001Date of Patent: March 30, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6712110Abstract: This invention is related to an apparatus for attaching resists and wafers to substrates, including: first and a second moving devices for moving substrates and wafers respectively; a first tank for containing an adhesive agent; a dispensing device which dispenses a predetermined amount of the adhesive agent at the central region of the wafer; a third moving device for placing the substrate on the wafer, a compressing device which compresses the substrate to squeeze out any possible air bubble existing within the adhesive agent between the substrate and the wafer; a second tank for containing the adhesive agent; a fourth moving device for moving the attached substrate and the wafer together to the second tank such that the complete area of the wafer at the side thereof opposite to the substrate is covered with the adhesive agent in an appropriate amount; a mold having a plurality of cavities arranged in a required pattern; a supplying device for providing a plurality of resists on the mold; a shake-and-load dType: GrantFiled: September 23, 2002Date of Patent: March 30, 2004Assignee: General Semiconductor of Taiwan, Ltd.Inventors: William John Nelson, Stanley Lai, Larry Shen, Jack Lin, Shyan-I Wu
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Patent number: 6710400Abstract: A method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.Type: GrantFiled: March 24, 2003Date of Patent: March 23, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6711132Abstract: A method and apparatus is provided for use in providing real-time, packet-switched service to an end-user over a cable data network. The method begins by transmitting over the cable data network a scheduled grant to an end-user gateway in accordance with an unsolicited grant service protocol. The grant authorizes the end-user gateway to transmit a data packet to a cable modem termination system (CMTS) located in the cable data network. Next, an adjustment is made to the time at which subsequent grants are transmitted. The adjustment, which is based on a response of the end-user gateway, is performed to reduce delay between a time when a subsequent data packet is generated and receipt of the subsequent grant.Type: GrantFiled: December 15, 2000Date of Patent: March 23, 2004Assignee: General Instrument CorporationInventor: David Beryl Lazarus
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Patent number: 6703588Abstract: A housing is provided for maintaining a planar lightguide circuit at a temperature within a predetermined temperature range independent of ambient temperature. The housing includes a planar heating arrangement supporting and in thermal contact with the planar lightguide circuit. Also included is a frame assembly having a first surface on which the planar heating arrangement is fixed. The frame assembly has at least one opening through which extends at least one optical fiber coupled to the planar lightguide circuit. An overmold, which is molded around the frame assembly, includes at least one strain relief member through which the optical fiber extends.Type: GrantFiled: May 31, 2002Date of Patent: March 9, 2004Assignee: Wavesplitter Technologies, Inc.Inventors: George F. Deveau, Francis A. Rotoloni
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Patent number: 6701056Abstract: A variably configurable and modular retainer for various discrete optical components (such as passive optical elements and mass fusion splices) is provided by a substantially planar base having an optical component support surface. Complementary finger pairs extend upwardly from the base. Each finger is disposed in an opposing arrangement with the other finger in the finger pair and is provided with an inner and outer surface. The respective opposing inner surfaces (each having a slightly concave profile) define an optical component receiving area that is sized and shaped to accommodate an optical component or splice. Each finger pair is resilient and laterally biased with a normal bias such that the inner surfaces are urged laterally inwardly and being movably outwardly for interlockingly engaging an optical component using snap-fit. The optical component may be thereby retained against the support surface of the base.Type: GrantFiled: January 2, 2002Date of Patent: March 2, 2004Assignee: Wavesplitter Technologies, Inc.Inventors: Denis Edward Burek, George Edwin Mock
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Patent number: 6689662Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.Type: GrantFiled: October 29, 2001Date of Patent: February 10, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6686244Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region.Type: GrantFiled: March 21, 2002Date of Patent: February 3, 2004Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6666588Abstract: A method is provided for assembling an optical collimator array. The method begins by directing light through a first optical collimator to produce a first optical output beam. The first collimator is supported by a first carrier element. The first collimator is rotated about its central longitudinal axis to adjust a position of the first optical output beam on a surface that intercepts the first optical output beam. The first carrier element is then rotated about a carrier axis perpendicular to the central longitudinal axis and in a plane containing the central longitudinal axis to further adjust the position of the first optical output beam on the surface. The first collimator continues to be rotated about these axes until the first optical output beam is located at a desired position on the surface, at which point the first optical collimator is secured to the first carrier element. Next, the first carrier element itself is secured to prevent rotation about the carrier axis.Type: GrantFiled: October 3, 2002Date of Patent: December 23, 2003Assignee: Photuris, Inc.Inventors: Neal H. Thorsten, Christopher S. Koeppen, Steven E. Parks, Wayne F. Thomas, Kenneth R. Mahon
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Patent number: 6660571Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a thin oxide layer and a polycrystalline semiconductor material (e.g., polysilicon) that includes a dopant of the second conductivity type.Type: GrantFiled: February 20, 2002Date of Patent: December 9, 2003Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 6660028Abstract: A method and apparatus is provided for determining an effective thermal mass of a patient. The effective thermal mass is employed to determine a gain factor used in a feedback control system controlling patient temperature. The method begins by inducing hypothermia or hyperthermia in at least a selected portion of the patient with a device having a heat transfer surface. Next, power is transferred between the device and the patient. A change in temperature over time, which arises in the selected portion of the patient, is measured while performing the step of inducing hypothermia or hyperthermia. Finally, an effective thermal mass is calculated based on the measured power and the measured temperature change over time.Type: GrantFiled: February 25, 2002Date of Patent: December 9, 2003Assignee: Innercool Therapies, Inc.Inventors: Michael Magers, Steven A. Yon