Abstract: One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die.

Abstract: Spring contact elements are fabricated at areas on an electronic component remote from terminals to which they are electrically connected. For example, the spring contact elements may be mounted to remote regions such as distal ends of extended tails (conductive lines) which extend from a terminal of an electronic component to positions which are remote from the terminals. In this manner, a plurality of substantially identical spring contact elements can be mounted to the component so that their free (distal) ends are disposed in a pattern and at positions which are spatially-translated from the pattern of the terminals on the component. The spring contact elements include, but are not limited to, composite interconnection elements and plated-up structures. The electronic component includes, but is not limited to, a semiconductor device, a memory chip, a portion of a semiconductor wafer, a space transformer, a probe card, a chip carrier, and a socket.