Abstract: An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket.

Abstract: The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

Abstract: A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output frequency. An active resistor is in parallel with the ring oscillator. The active resistor has a resistor and an n-channel transistor in series between the oscillator-power node and ground. The n-channel transistor has a fixed bias voltage on its gate and is non-linear. The non-linear effective resistance of the n-channel transistor improves overall linearity of the ring oscillator. The parallel effective resistance of the active resistor lowers overall effective resistance of the ring oscillator.

Abstract: A test manager software program includes an interactive test graphical-user-interface (GUI) for testing network devices using high-level networking commands. The test GUI allows the test engineer user to enter high-level commands such as Simple Networking Management Protocol (SNMP) commands that read values in a management information database in a network device under test. The high-level commands can be sent from the test manager using a command-line interface (CLI) in a telnet session opened to the network device during testing. The user specifies high-level test, analyze, and restore commands in test cases that are collected into test suites. Rules for logging on to the network device under test are stored that include expected prompts from the network device and user responses such as passwords. Addresses of the network device under test can be re-mapped for testing other devices so the test suites can be reused.

Abstract: An oscillator inverter circuit has an input at a first crystal node and drives a second crystal node of a crystal oscillator. The first node is lightly loaded by a gate of an input transistor that generates a buffered node. The buffered node voltage is converted to a varying current by a converter transistor. Another varying current through upper and lower amplifier transistors are mirrored to upper and lower current mirror transistors. The gate and drain of the lower current mirror transistor are connected to the gate of an output transistor that pulls down the second node with low impedance. The drain of the upper current mirror transistor diverts current from an output current source, changing pull-up current to the second node through a p-channel transistor. An input resistor between the first node and the buffered node provides a DC bias but blocks AC oscillation signals.

Abstract: An electronic exchange creates and distributes value among trading partners in a trade. Trading agents for the trading partners use a value manager to store true values for a trading element in the trade. The true values are the values perceived by the trading partner, but are not shown to other trading partners. These true values vary with attributes of the trading element. The attributes modify the trading element and are valued differently by different trading partners. A trade manager receives offers from trading agents. The offers are sent with the true values and the attribute values. The trade manager compares true values of buyers and sellers across a range of attribute values. Net values are computed as the difference of a buyers' sum and a sellers' sum. The buyers' sum is the sum of all true values from buyer trading agents, while the sellers' sum is the sum of the true values of all seller trading agents. The trade manager finds a set of attribute values that has a maximum net value.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: Bayer-pattern pixels captured by an image sensor have only one of the three primary colors (RGB) per pixel location. Rather than interpolate the Bayer-pattern to generate the missing RGB color components for each pixel location, a direct conversion is performed to YUV pixels. A luminance calculator receives a 3×3 block of Bayer-pattern pixels and generates a luminance (Y) pixel for the center pixel location. Different coefficients are multiplied by each of the 9 Bayer-pattern pixels before summing to produce the center Y pixel, depending on the pattern location. A chrominance calculator first receives a 3×3 block of Y pixels generated by the luminance calculator. The 9 Y pixels are averaged to produce an average luminance. Two red or blue pixels in the 3×3 block are averaged and the average luminance subtracted. Then a constant is multiplied to generate the U and V pixels. Intermediate interpolated RGB avoided.

Abstract: A flash-card exchanger has two modes of operation. When a host personal computer (PC) is connected to a Universal-Serial-Bus (USB) connector, the flash-card exchanger operates in a card reader mode, allowing the host to read data from removable flash-memory cards inserted into connector slots of the flash-card exchanger. When the host PC is not connected, a USB flash-memory thumb or key-chain drive can be inserted into a second USB connector. A USB dual-mode microcontroller acts as a USB host, reading data from the removable flash-memory card and writing the data to the USB-memory key drive using USB packets. Since the USB-memory key drive is small and removable, the user can upgrade to larger storage capacities by plugging in a larger-capacity USB-memory key drive. A flash-exchanger program executing on the USB dual-mode microcontroller copies data from an input-output bus and generates USB packets to the USB-memory key drive.

Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-input voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A feature phone has a base-band processor and an applications processor that communicate with each other by emulating an internal Ethernet within the phone. TCP/IP stacks in each processor receive data from high-level applications for transmission to the other processor. Ethernet-emulating drivers are called by the IP layers. An Ethernet-emulating transmit driver writes IP-packet data to a shared memory and sends an interrupt to the other processor, which activates a receive routine that reads the IP packet data from the shared memory and sends it up through the TCP/IP stack. There is no twisted-pair cable or other media since the shared memory acts as the transfer media. A shared mailbox holds the packet length and sends an interrupt to one processor when written, while a general-purpose input-output GPIO module sends an interrupt to the other processor. The internal emulated-Ethernet is entirely within the phone and separate from cellular networks.

Abstract: A levered handle has an elongated slot that allows the levered handle to both slide and pivot over a pivot axis. The levered handle is slid over the pivot axis to allow a notch engager to engage a notch on a memory module. Then the notch engager is forced downward as the levered handle pivots upward about the pivot axis, causing a downward force to be applied to the notch on the memory module. This forces the memory module into a memory module socket. The memory module socket requires a reduced insertion force because the notch engager on the levered handle engages the notch on the memory module and applies downward pressure. A levered handle without the elongated slot can slide along the pivot axis perpendicular to the memory module to engage the notch. Both ejection and insertion forces can be reduced.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.

Abstract: A display has an array of Micro-Electro-Mechanical Switches (MEMS) display elements on a substrate such as glass. Rather than directly drive all columns of the MEMS display elements from off-substrate column drivers, column mux logic is placed on the substrate. The column mux logic uses MEMS contact-switch elements that have additional contact electrodes that touch and make electrical connection when the MEMS switch is closed, but do not touch and isolate the contact electrodes from each other when the MEMS switch is open. Smaller data words of column data is successively loaded into and stored by the MEMS column-mux, which then drives the columns of the display array. The smaller data words require fewer off-substrate connections than if all columns were driven by the off-substrate drivers. An intermediate holding voltage is applied to store column data in the column mux. Off-substrate interconnect is further reduced using on-substrate row-mux MEMS.

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract: A memory module has improved signal propagation delays for signals externally driven such as from a motherboard. Reflections from junctions of wiring traces on the memory module are reduced or eliminated. An input buffer or register receives a signal from the motherboard and splits the signal to drive two outputs to two separate traces. Each trace is enlarged in width or thickness, such as by using a double-width wiring trace. At the fare end of each double-width trace, a junction is made to two minimum-width traces that connect to small stub traces to DRAM inputs. Reflections from the junction are eliminated or reduced by trace-impedance matching, since the input impedance of the double-width trace from the input buffer is about the same as the combined impedance of the two minimum-width traces. Trace-input matching and input buffering can improve signal integrity and overall propagation delay.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-in-put voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: Memory chips are assembled into a stack with an insertion-pin frame between pins of two stacked memory chips. The insertion-pin frame is not bent or formed into 3-dimensional shapes but is flat, improving use in standard surface-mount processes such as solder printing onto the insertion-pin frame. Flat insertion pins held to the flat insertion-pin frame by necks are soldered to top shoulders of pins on a lower chip. Then bottom feet of pins of an upper chip are soldered to the insertion pins. The necks are punched away or broken to release the insertion-pin frame from the insertion pins that are soldered to the assembled stacked chips. An insulated wire jumper can be placed under the pins to jumper chip-select connections, or a bridge between insertion pins can be formed from the insertion-pin frame. Holding tabs to the bridge are removed with the insertion pins or by punching.

Abstract: A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors—p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors drive through a transmission gate to a self-bias node. The second amplifier receives the second input signal and has the same structure, with one branch driving the self-bias voltage through another transmission gate, and another branch driving a complementary differential output. The bias-generating branches use smaller transistors so that only a small current is used to generate the self-bias voltage. The self-bias node is fed to the gates of current source and sink transistors.