Abstract: A voltage down converter with hysteresis generator combining a hysteresis signal to a reference voltage and an output voltage feedback signal applied to a comparator. The hysteresis generator is coupled to a control signal giving advance notice of when a high current load is to be activated. The hysteresis signal is switched to a first state prior to the high current load activation, and switched to a second state after the high current load activation. In the first state, the hysteresis voltage is added to a reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.

Abstract: A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a “coherency tag” to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques.

Abstract: A tool for removing tie down cables from a center beam rail car loaded with cargo, the apparatus comprising a support beam having a width selected to be greater than the span between a number of tie down cables on the center beam rail car. A plurality of hook-shaped cable claws are rigidly attached in a spaced apart, downwardly extending manner to the support beam. At least one lift sleeve rigidly attached to the support beam and having a receiving end for attaching to an external lift mechanism.

Abstract: A navigation system for a hierarchy of objects displayed by a computing system are rapidly navigated first by an automatic explosion module for exploding a displayed node of the hierarchy in response to a first characteristic stroke by a pointer control device while the pointer is within the boundary of the displayed node. In addition, an implosion module implodes nodes branching from a displayed node of the hierarchy in response to a second characteristic stroke by the pointer control device while the pointer is within the boundary of the displayed node. The first characteristic stroke by the pointer control device is movement of the pointer controlled by the pointer control device within the boundaries of the displayed node. The second characteristic stroke by the pointer control device is a mouse click while the pointer is within the boundaries of the displayed node or object. A keystroke module sets the level of further explosion of the node when the displayed node is exploded by the explosion module.

Abstract: A self calibrating zero compensation circuit for a fluxgate compass comprising a toroidal core; a drive winding coupled to said core, and at least one and preferably two secondary sensing windings coupled to said core comprises a continuously operating demodulator coupled to the sensing windings and an intermittently operated drive signal fed to the drive winding. A microprocessor is coupled to the demodulator output through an analog to digital converter. The microprocessor provides alternatingly to the drive winding a drive signal for a first period of time and prevents transmission of the drive signal for a second, preferably equal period of time. During the second period of time, the sensing windings and the demodulator provide an output signal to said microprocessor representing the zero signal reference. The demodulator output during the first period of time represents the magnetic field signal from the compass.

Abstract: A reference voltage generator for producing a reference voltage that is a preselected amount below a power supply voltage. A reference voltage source produces a first reference voltage that is VREF above the ground potential. A first load device coupled to the ground node and generates an internal reference signal that is determined by the magnitude of current flowing in the first load device. A differential amplifier produces a signal determined by a difference between the signals on the first and second inputs. A current regulating switch having a control node coupled to the differential amplifier output, and coupled to determine the current through the first load device. A second load device coupled in series with the first load device and coupled to the power supply node has an impedance selected to cause the second load device to generate the second reference voltage.

Abstract: A memory device, and an associated method, contain at least two memory arrays and a single decoder shared by the memory arrays. When data is to be accessed from selected memory locations of one of the memory arrays, the non-selected memory array is inactivated by precharging the bit lines of the array to a common voltage with the data input and/or output buses for that array, thereby allowing the decoder to select the inactive array without harm, and thereby preventing the need for additional decoder circuitry to discriminate between the arrays. The array containing the selected memory locations remains active, thereby permitting accessing of the memory locations therein.

Abstract: The present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit generating a precharge (PC) signal and a reset regulator signal in response to the enable regulator signal. A pump clock unit receives a master clock signal and generating a plurality of pump clock signals. A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals, and coupled to the an output terminal coupled to produce an output signal (VPUMP). A regulator unit is coupled to receive the VPUMP signal, the PC signal, the reference signal and the enable regulator signal, where the regulator unit is responsive to the enable regulator signal to operate in either a precharge mode or a regulation mode.

Abstract: A paint can rim seal and groove protector that is simple and inexpensive in its manufacture and construction and easily allows the pouring of paint or other liquid from a can. A seal for a can rim includes a deformable rim seal having a width defined by an interior diameter smaller than the can rim and an exterior diameter larger than the can rim. A pressure sensitive releasable adhesive coating is provided on one surface of the deformable rim seal. In operation, the rim seal is aligned with the can rim with the adhesive coated side down. The rim seal is then removably placed on the rim. Interior and exterior edges of the rim seal are manually bent down to adhesively seal against the interior and exterior sidewalls of the can.

Abstract: A switch including a plurality of input/output (I/O) ports and a switching element programmably coupling a first of the I/O ports with a second of the I/O ports. An analysis device is associated with the first I/O port measuring at least one data traffic parameter specific to data traffic between the first I/O port and the second I/O port.

Abstract: A nanocomposite structure comprising a nanostructured filler or carrier intimately mixed with a matrix, and methods of making such a structure. The nanostructured filler has a domain size sufficiently small to alter an electrical, magnetic, optical, electrochemical, chemical, thermal, biomedical, or tribological property of either filler or composite by at least 20%.

Abstract: Methods and devices for transforming less desirable chemical species into more desirable or useful chemical forms are disclosed. The specifications can be used to treat pollutants into more benign compositions and to produce useful chemicals from raw materials and wastes. The methods and devices disclosed utilize electrical current induced by electromagnetic field and high surface area formulations. The invention can also be applied to improve the performance of existing catalysts and to prepare novel devices.

Abstract: Methods of monitoring environmental variables in general and chemical composition in particular, and sensors for such monitoring. These low-cost sensors comprised multiple layers in a laminated stack. Very high numbers of sensing layers (e.g., 500) may be incorporated into a single laminated sensor device. The sensors may signal changes in environmental state such as chemical composition due to changes in sensor properties such as resistivity, capacitance, inductance, permittivity, permeability, refractive index, chromaticity, transparency to light, reflection characteristics, resonance frequency, and/or magnetic characteristics.

Abstract: A memory device including a plurality of sense amplifiers distributed about an integrated circuit chip, where each sense amplifier has a power node for receiving current. A conductor couples the power nodes of a number of sense amplifiers together. A low-impedance power supply conductor extends to each sense amplifier and a local drive transistor is provided for each sense amplifier. A timer unit generates an output signal controlling the local drive transistors. A first component within the timer unit causes the output to change from a first logic level towards a second logic level at a first rate while a second component within the timer unit causes the output to change at a second rate, wherein the second rate is greater than the first rate.

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A method for aggregating distributed information from a plurality of data sources each having an address. A plurality of user criteria are received and site specific information describing idiosyncrasies of each data source are stored. A plurality of query messages are generated based upon the received criteria and the stored idiosyncrasy information. For each query message, a communication packet is generated comprising the query message and an address for the corresponding data source. A plurality of communication ports are created with each port associated with one of the communication packets. Each communication packet is sent over its associated port to the addressed data source.

Abstract: A method and apparatus for the establishment of dynamic Enterprise System Connection ("ESCON") connections over a Fibre Channel connection allows a port state machine (or port module) to request dynamic ESCON connections from the exchange context of the Fibre Channel frame and to implement dynamic linking of the Fibre Channel exchanges to ESCON ports while also linking and monitoring the status of these connections for all subsequent frames associated on a particular exchange. In a particular embodiment, the method and apparatus provides the ability to establish dynamic connections through an ESCON Director switch based off of the Originator Exchange Identifier ("OX.sub.-- ID") of the FC-2 header and information contained in the FC-4 header of the Fibre Channel frame. Once a connection path has been established for a particular OX.sub.-- ID, that connection is maintained until the exchange is terminated.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced.

Abstract: A switch having a plurality of input/output (I/O) ports and a crossbar device programmably coupling a first of the I/O ports with a second of the I/O ports. A plurality of port request controllers (PRCs) are coupled such that each PRC is associated with one of the I/O ports. A plurality of serial request busses are arranged such that each serial request bus couples each PRC with its associated port. A plurality of serial response busses are coupled such that each serial response bus coupling each PRC with its associated PRC. In operation, the serial request and response busses operate independently in a non-blocking fashion to process connection and clear requests in parallel.